TY - GEN
T1 - Reducing the energy cost of irregular code bases in soft processor systems
AU - Arora, Manish
AU - Sampson, Jack
AU - Goulding-Hotta, Nathan
AU - Babb, Jonathan
AU - Venkatesh, Ganesh
AU - Taylor, Michael Bedford
AU - Swanson, Steven
PY - 2011/6/17
Y1 - 2011/6/17
N2 - This paper describes an architecture and FPGA synthesis tool chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism. Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5x for the code they target and 2.8x for whole applications.
AB - This paper describes an architecture and FPGA synthesis tool chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism. Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5x for the code they target and 2.8x for whole applications.
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U2 - 10.1109/FCCM.2011.45
DO - 10.1109/FCCM.2011.45
M3 - Conference contribution
AN - SCOPUS:79958695609
SN - 9780769543017
T3 - Proceedings - IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011
SP - 210
EP - 213
BT - Proceedings - IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011
T2 - 19th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011
Y2 - 1 May 2011 through 3 May 2011
ER -