Reliability-aware SOC voltage Islands partition and floorplan

Shengqi Yang, Wayne Wolf, Vijaykrishnan Narayanan, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip design, for the first time, is illustrated. Voltage island partitioning and floorplanning for System-On-a-Chip (SOC) design is used as a case study for this reliability aware methodology. The proposed methodology partitions all SOC components into different voltage islands with power reduction and guaranteed system reliability. Experiments show that for a typical SOC the algorithm execution time is within several minutes while achieving 12% to 23% power reduction. Extended SOC algorithm partitions and floorplanns the voltage islands within 2.5 to 29.7 minutes and achieved 9.74% to 18.50% power reduction.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages343-348
Number of pages6
Volume2006
DOIs
StatePublished - Oct 9 2006
EventIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany
Duration: Mar 2 2006Mar 3 2006

Other

OtherIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
CountryGermany
CityKlarlsruhe
Period3/2/063/3/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Yang, S., Wolf, W., Narayanan, V., & Xie, Y. (2006). Reliability-aware SOC voltage Islands partition and floorplan. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (Vol. 2006, pp. 343-348). [1602462] https://doi.org/10.1109/ISVLSI.2006.79