Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction

C. Radhakrishnan, W. K. Jenkins

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

System architectures for fault tolerant computing and signal processing can be based on either modular hardware redundancy or arithmetic error detection and correction coding. Traditional triple modular redundancy (TMR) is very general but often leads to hardware intensive high-power implementations. In contrast, fault tolerant designs that rely on arithmetic coding reduce hardware requirements but result in higher computational requirements that must be implemented in a separate decoding unit. This paper proposes a hybrid combination of redundant hardware modules and arithmetic (algorithmic) error detection to produce efficient and reliable designs for transform domain adaptive filters.

Original languageEnglish (US)
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
StatePublished - 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: Aug 7 2011Aug 10 2011

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period8/7/118/10/11

Fingerprint

Error detection
Adaptive filters
Error correction
Hardware
Redundancy
Fault tolerant computer systems
Decoding
Signal processing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Radhakrishnan, C., & Jenkins, W. K. (2011). Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026503] https://doi.org/10.1109/MWSCAS.2011.6026503
Radhakrishnan, C. ; Jenkins, W. K. / Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction. 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011.
@inproceedings{ed6036895d7a4ca095d4f0fdfdac235f,
title = "Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction",
abstract = "System architectures for fault tolerant computing and signal processing can be based on either modular hardware redundancy or arithmetic error detection and correction coding. Traditional triple modular redundancy (TMR) is very general but often leads to hardware intensive high-power implementations. In contrast, fault tolerant designs that rely on arithmetic coding reduce hardware requirements but result in higher computational requirements that must be implemented in a separate decoding unit. This paper proposes a hybrid combination of redundant hardware modules and arithmetic (algorithmic) error detection to produce efficient and reliable designs for transform domain adaptive filters.",
author = "C. Radhakrishnan and Jenkins, {W. K.}",
year = "2011",
doi = "10.1109/MWSCAS.2011.6026503",
language = "English (US)",
isbn = "9781612848570",
booktitle = "54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011",

}

Radhakrishnan, C & Jenkins, WK 2011, Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026503, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 8/7/11. https://doi.org/10.1109/MWSCAS.2011.6026503

Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction. / Radhakrishnan, C.; Jenkins, W. K.

54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026503.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction

AU - Radhakrishnan, C.

AU - Jenkins, W. K.

PY - 2011

Y1 - 2011

N2 - System architectures for fault tolerant computing and signal processing can be based on either modular hardware redundancy or arithmetic error detection and correction coding. Traditional triple modular redundancy (TMR) is very general but often leads to hardware intensive high-power implementations. In contrast, fault tolerant designs that rely on arithmetic coding reduce hardware requirements but result in higher computational requirements that must be implemented in a separate decoding unit. This paper proposes a hybrid combination of redundant hardware modules and arithmetic (algorithmic) error detection to produce efficient and reliable designs for transform domain adaptive filters.

AB - System architectures for fault tolerant computing and signal processing can be based on either modular hardware redundancy or arithmetic error detection and correction coding. Traditional triple modular redundancy (TMR) is very general but often leads to hardware intensive high-power implementations. In contrast, fault tolerant designs that rely on arithmetic coding reduce hardware requirements but result in higher computational requirements that must be implemented in a separate decoding unit. This paper proposes a hybrid combination of redundant hardware modules and arithmetic (algorithmic) error detection to produce efficient and reliable designs for transform domain adaptive filters.

UR - http://www.scopus.com/inward/record.url?scp=80053625957&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80053625957&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2011.6026503

DO - 10.1109/MWSCAS.2011.6026503

M3 - Conference contribution

SN - 9781612848570

BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011

ER -