Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction

C. Radhakrishnan, W. K. Jenkins

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

System architectures for fault tolerant computing and signal processing can be based on either modular hardware redundancy or arithmetic error detection and correction coding. Traditional triple modular redundancy (TMR) is very general but often leads to hardware intensive high-power implementations. In contrast, fault tolerant designs that rely on arithmetic coding reduce hardware requirements but result in higher computational requirements that must be implemented in a separate decoding unit. This paper proposes a hybrid combination of redundant hardware modules and arithmetic (algorithmic) error detection to produce efficient and reliable designs for transform domain adaptive filters.

Original languageEnglish (US)
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
StatePublished - 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: Aug 7 2011Aug 10 2011

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period8/7/118/10/11

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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