Reshaping cache misses to improve row-buffer locality in multicore systems

Wei Ding, Jun Liu, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Optimizing cache locality has always been important since the emergence of caches, and numerous cache locality optimization schemes have been published in compiler literature. However, in modern architectures, cache locality is not the only factor that determines memory system performance. Many emerging multicores employ banked memory systems and each bank is attached a row-buffer that holds the most-recently accessed memory row (page). A last-level cache miss that also misses in the row-buffer can experience much higher latency than a cache miss that hits in the row-buffer. Consequently, optimizing for row-buffer locality can be as important as optimizing for cache locality. Targeting emerging multicores and multithreaded applications, this paper presents a compiler-directed row-buffer locality optimization strategy. This strategy modifies the memory layout of data to increase the number of row-buffer hits without increasing the number of misses in the on-chip cache hierarchy. We implemented our proposed optimization strategy in an open-source compiler and tested its effectiveness in improving the row-buffer performance using a set of multithreaded applications. Our results indicate that the proposed approach improves the average data access latency by about 29%, and this translates, on average, to about 15% improvement in execution time.

Original languageEnglish (US)
Title of host publicationPACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques
Pages235-244
Number of pages10
DOIs
StatePublished - 2013
Event22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013 - Edinburgh, United Kingdom
Duration: Sep 7 2013Sep 11 2013

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Other

Other22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013
CountryUnited Kingdom
CityEdinburgh
Period9/7/139/11/13

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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