Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Yih Wang, Umut Arslan, Nabhendra Bisnik, Ruth Brain, Swaroop Ghosh, Fatih Hamzaoglu, Nick Lindert, Mesut Meterelliyoz, Joodong Park, Shigeki Tomishima, Kevin Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

Original languageEnglish (US)
Title of host publication2013 IEEE International Electron Devices Meeting, IEDM 2013
DOIs
StatePublished - Dec 1 2013
Event2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
Duration: Dec 9 2013Dec 11 2013

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2013 IEEE International Electron Devices Meeting, IEDM 2013
CountryUnited States
CityWashington, DC
Period12/9/1312/11/13

Fingerprint

CMOS
systems-on-a-chip
optimization
Networks (circuits)
Noise abatement
noise reduction
manufacturing
System-on-chip

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Wang, Y., Arslan, U., Bisnik, N., Brain, R., Ghosh, S., Hamzaoglu, F., ... Zhang, K. (2013). Retention time optimization for eDRAM in 22nm tri-gate CMOS technology. In 2013 IEEE International Electron Devices Meeting, IEDM 2013 [6724595] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724595
Wang, Yih ; Arslan, Umut ; Bisnik, Nabhendra ; Brain, Ruth ; Ghosh, Swaroop ; Hamzaoglu, Fatih ; Lindert, Nick ; Meterelliyoz, Mesut ; Park, Joodong ; Tomishima, Shigeki ; Zhang, Kevin. / Retention time optimization for eDRAM in 22nm tri-gate CMOS technology. 2013 IEEE International Electron Devices Meeting, IEDM 2013. 2013. (Technical Digest - International Electron Devices Meeting, IEDM).
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abstract = "A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.",
author = "Yih Wang and Umut Arslan and Nabhendra Bisnik and Ruth Brain and Swaroop Ghosh and Fatih Hamzaoglu and Nick Lindert and Mesut Meterelliyoz and Joodong Park and Shigeki Tomishima and Kevin Zhang",
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Wang, Y, Arslan, U, Bisnik, N, Brain, R, Ghosh, S, Hamzaoglu, F, Lindert, N, Meterelliyoz, M, Park, J, Tomishima, S & Zhang, K 2013, Retention time optimization for eDRAM in 22nm tri-gate CMOS technology. in 2013 IEEE International Electron Devices Meeting, IEDM 2013., 6724595, Technical Digest - International Electron Devices Meeting, IEDM, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, United States, 12/9/13. https://doi.org/10.1109/IEDM.2013.6724595

Retention time optimization for eDRAM in 22nm tri-gate CMOS technology. / Wang, Yih; Arslan, Umut; Bisnik, Nabhendra; Brain, Ruth; Ghosh, Swaroop; Hamzaoglu, Fatih; Lindert, Nick; Meterelliyoz, Mesut; Park, Joodong; Tomishima, Shigeki; Zhang, Kevin.

2013 IEEE International Electron Devices Meeting, IEDM 2013. 2013. 6724595 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Arslan, Umut

AU - Bisnik, Nabhendra

AU - Brain, Ruth

AU - Ghosh, Swaroop

AU - Hamzaoglu, Fatih

AU - Lindert, Nick

AU - Meterelliyoz, Mesut

AU - Park, Joodong

AU - Tomishima, Shigeki

AU - Zhang, Kevin

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N2 - A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

AB - A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

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Wang Y, Arslan U, Bisnik N, Brain R, Ghosh S, Hamzaoglu F et al. Retention time optimization for eDRAM in 22nm tri-gate CMOS technology. In 2013 IEEE International Electron Devices Meeting, IEDM 2013. 2013. 6724595. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724595