We present a novel 3D-SRAM cells using a monolithic 3D integration technology for realizing both robustness of the cell and in-memory Boolean logic computing capability. The proposed two-layer cell designs make use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, and XNOR/XOR) or enable content addressability without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes, and we evaluate the energy efficiency of our proposed design. We show that the assist techniques improve SRAM read stability by 2.2× and increase the write margin by 17.6% while staying within the SRAM footprint. By the virtue of increased robustness, the cell enables seamless operation at lower supply voltages; and thereby, ensures energy efficiency. Energy delay product reduces by 1.6× over standard 6T SRAM with a faster data access. When computing bulk In-memory operations, 6.5× energy saving is achieved as compared to computing outside the memory system.
|Original language||English (US)|
|Number of pages||13|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Jul 2019|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering