Robust CMOS logic technique for building high frequency circuits with efficient pipelining

Eric Gayles, Kevin Acken, Robert M. Owens, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

Abstract

Current fine grain pipelining techniques, such as True Single-Phase, allow for high frequency circuit design at the cost of significant latency per operation. On the other hand, low latency designs require complex circuitry within pipeline stages, which is not feasible when designing high clock frequency systems. In this paper, we propose a novel CMOS circuit technique that allows both high frequency circuits and low cycle latency per operation. Our technique differs from other logic families that have attempted to provide the same advantages by being more robust in the presence of process variations and signal coupling. To show the feasibility of our circuit technique, we also present a 64 bit carry-lookahead adder using this circuit technique that is capable of calculating a 64 bit add every 2.0 nanoseconds.

Original languageEnglish (US)
Pages (from-to)168-172
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 1997
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: Sep 7 1997Sep 10 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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