Role of metal-1 layout in plasma processing-induced damage

Motasim G. El Hassan, Osama O. Awadelkarim, Jim Werking

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

The possible role of the interconnect layout in plasma processing-induced damage is Investigated. Two sets of LDD n-MOSFETs with different metal 1 layouts are examined and compared to devices with larger metal gate antennae. The results clearly indicate that interconnect layouts may invoke MOSFET's degradation mechanisms different than the conventional plasma processing-induced capacitive charging of the gate oxide by gate antenna.

Original languageEnglish (US)
Pages251-254
Number of pages4
DOIs
StatePublished - Jan 1 1997
EventProceedings of the 1997 2nd International Symposium on Plasma Process-Induced Damage - Monterey, CA, USA
Duration: May 13 1997May 14 1997

Other

OtherProceedings of the 1997 2nd International Symposium on Plasma Process-Induced Damage
CityMonterey, CA, USA
Period5/13/975/14/97

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    El Hassan, M. G., Awadelkarim, O. O., & Werking, J. (1997). Role of metal-1 layout in plasma processing-induced damage. 251-254. Paper presented at Proceedings of the 1997 2nd International Symposium on Plasma Process-Induced Damage, Monterey, CA, USA, . https://doi.org/10.1109/ppid.1997.596763