Runtime code parallelization for on-chip multiprocessors

M. Kandemir, W. Zhang, M. Karakoy

Research output: Contribution to journalConference article

4 Scopus citations

Abstract

Chip multiprocessing (or multiprocessor system-on-a-chip) is a technique that combines two or more processor cores on a single piece of silicon to enhance computing performance. An important problem to be addressed in executing applications on an on-chip multiprocessor environment is to select the most suitable number of processors to use for a given objective function (e.g., minimizing execution time or energy-delay product) under multiple constraints. Previous research proposed an ILP-based solution to this problem that is based on exhaustive evaluation of each nest under all possible processor sizes. In this paper, we take a different approach and propose a pure runtime strategy for determining the best number of processors to use at runtime. This approach is more general than static techniques and can be applicable in situations where the latter cannot be.

Original languageEnglish (US)
Article number1253660
Pages (from-to)510-515
Number of pages6
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
StatePublished - Dec 1 2003
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany
Duration: Mar 3 2003Mar 7 2003

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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