Scheduling reusable instructions for power reduction

J. S. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82% of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72% in the instruction cache, 33% in the branch predictor, and 21% in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
EditorsG. Gielen, J. Figueras
Pages148-153
Number of pages6
DOIs
StatePublished - Jul 12 2004
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: Feb 16 2004Feb 20 2004

Publication series

NameProceedings - Design, Automation and Test in Europe Conference and Exhibition
Volume1

Other

OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
CountryFrance
CityParis
Period2/16/042/20/04

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Hu, J. S., Vijaykrishnan, N., Kim, S., Kandemir, M., & Irwin, M. J. (2004). Scheduling reusable instructions for power reduction. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 (pp. 148-153). (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 1). https://doi.org/10.1109/DATE.2004.1268841