Scheduling reusable instructions for power reduction

J. S. Hu, Vijaykrishnan Narayanan, S. Kim, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82% of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72% in the instruction cache, 33% in the branch predictor, and 21% in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
EditorsG. Gielen, J. Figueras
Pages148-153
Number of pages6
DOIs
StatePublished - Jul 12 2004
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: Feb 16 2004Feb 20 2004

Publication series

NameProceedings - Design, Automation and Test in Europe Conference and Exhibition
Volume1

Other

OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
CountryFrance
CityParis
Period2/16/042/20/04

Fingerprint

Pipelines
Scheduling
Decoding
Costs

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Hu, J. S., Narayanan, V., Kim, S., Kandemir, M., & Irwin, M. J. (2004). Scheduling reusable instructions for power reduction. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 (pp. 148-153). (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 1). https://doi.org/10.1109/DATE.2004.1268841
Hu, J. S. ; Narayanan, Vijaykrishnan ; Kim, S. ; Kandemir, Mahmut ; Irwin, Mary Jane. / Scheduling reusable instructions for power reduction. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. editor / G. Gielen ; J. Figueras. 2004. pp. 148-153 (Proceedings - Design, Automation and Test in Europe Conference and Exhibition).
@inproceedings{ce0002f023324ceb89762b7ac5a141b8,
title = "Scheduling reusable instructions for power reduction",
abstract = "In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82{\%} of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72{\%} in the instruction cache, 33{\%} in the branch predictor, and 21{\%} in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.",
author = "Hu, {J. S.} and Vijaykrishnan Narayanan and S. Kim and Mahmut Kandemir and Irwin, {Mary Jane}",
year = "2004",
month = "7",
day = "12",
doi = "10.1109/DATE.2004.1268841",
language = "English (US)",
isbn = "0769520855",
series = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition",
pages = "148--153",
editor = "G. Gielen and J. Figueras",
booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04",

}

Hu, JS, Narayanan, V, Kim, S, Kandemir, M & Irwin, MJ 2004, Scheduling reusable instructions for power reduction. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 148-153, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, France, 2/16/04. https://doi.org/10.1109/DATE.2004.1268841

Scheduling reusable instructions for power reduction. / Hu, J. S.; Narayanan, Vijaykrishnan; Kim, S.; Kandemir, Mahmut; Irwin, Mary Jane.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. ed. / G. Gielen; J. Figueras. 2004. p. 148-153 (Proceedings - Design, Automation and Test in Europe Conference and Exhibition; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Scheduling reusable instructions for power reduction

AU - Hu, J. S.

AU - Narayanan, Vijaykrishnan

AU - Kim, S.

AU - Kandemir, Mahmut

AU - Irwin, Mary Jane

PY - 2004/7/12

Y1 - 2004/7/12

N2 - In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82% of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72% in the instruction cache, 33% in the branch predictor, and 21% in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.

AB - In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82% of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72% in the instruction cache, 33% in the branch predictor, and 21% in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.

UR - http://www.scopus.com/inward/record.url?scp=3042604822&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=3042604822&partnerID=8YFLogxK

U2 - 10.1109/DATE.2004.1268841

DO - 10.1109/DATE.2004.1268841

M3 - Conference contribution

SN - 0769520855

SN - 9780769520858

T3 - Proceedings - Design, Automation and Test in Europe Conference and Exhibition

SP - 148

EP - 153

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04

A2 - Gielen, G.

A2 - Figueras, J.

ER -

Hu JS, Narayanan V, Kim S, Kandemir M, Irwin MJ. Scheduling reusable instructions for power reduction. In Gielen G, Figueras J, editors, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. 2004. p. 148-153. (Proceedings - Design, Automation and Test in Europe Conference and Exhibition). https://doi.org/10.1109/DATE.2004.1268841