SEAT-LA: A soft error analysis tool for combinational logic

R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

95 Scopus citations

Abstract

Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft error rates (SER) in logic circuits. In this paper, we propose a new approach, which can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates using our approach compared to the estimates obtained using circuit level simulations is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Pages499-502
Number of pages4
DOIs
StatePublished - Sep 18 2006
Event19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design - Hyderabad, India
Duration: Jan 3 2006Jan 7 2006

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2006
ISSN (Print)1063-9667

Other

Other19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
CountryIndia
CityHyderabad
Period1/3/061/7/06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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