Self-aligned-gate PEALD ZnO TFT circuits

Devin A. Mourey, Dalong A. Zhao, Thomas N. Jackson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin film transistors (TFTs) with a self-aligned-gate process to fabricate high speed circuits. Sputter deposited ZnO films have been widely studied, but there have been few reports of dense thin films and high performance devices and circuits. Atomic layer deposition (ALD) of ZnO has been shown to be a very uniform and conformal process, but ALD ZnO films typically have high background carrier concentration and require doping compensation for enhancement-mode TFTs. PEALD provides the uniform conformal coating of ALD and enhancement-mode devices from uncompensated films. Our PEALD ZnO TFTs have linear field-effect mobility >20 cm2/V·s and saturation field-effect mobility >30 cm2/V·s and PEALD ring oscillators with beta ratio ∼5, channel length ∼2.8 μm, and ∼1.5 μm gate-source/drain overlap operate at ∼25 ns/stage. Recently, scaled indium-galliumzinc oxide ring oscillator circuits on silicon substrates (0.5 μm channel length, and 0.5 μm overlap) were reported to operate at ∼7 ns/stage with a saturated-load inverter design, and < 1 ns/stage with a novel bootstrapped inverter design [1]. The speed of our previous PEALD circuits [2] was largely limited by the parasitic capacitance between the gate and drain, and a self-aligned-gate process would provide higher speed devices and circuits. Here we have report a simple self-aligned-gate process for ZnO TFTs and high speed circuits.

Original languageEnglish (US)
Title of host publication67th Device Research Conference, DRC 2009
Pages187-188
Number of pages2
DOIs
StatePublished - Dec 11 2009
Event67th Device Research Conference, DRC 2009 - University Park, PA, United States
Duration: Jun 22 2009Jun 24 2009

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Other

Other67th Device Research Conference, DRC 2009
CountryUnited States
CityUniversity Park, PA
Period6/22/096/24/09

Fingerprint

Atomic layer deposition
Thin film transistors
Plasmas
Networks (circuits)
Indium
Carrier concentration
Capacitance
Doping (additives)
Thin films
Silicon
Coatings
Oxides
Substrates

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Mourey, D. A., Zhao, D. A., & Jackson, T. N. (2009). Self-aligned-gate PEALD ZnO TFT circuits. In 67th Device Research Conference, DRC 2009 (pp. 187-188). [5354943] (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2009.5354943
Mourey, Devin A. ; Zhao, Dalong A. ; Jackson, Thomas N. / Self-aligned-gate PEALD ZnO TFT circuits. 67th Device Research Conference, DRC 2009. 2009. pp. 187-188 (Device Research Conference - Conference Digest, DRC).
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Mourey, DA, Zhao, DA & Jackson, TN 2009, Self-aligned-gate PEALD ZnO TFT circuits. in 67th Device Research Conference, DRC 2009., 5354943, Device Research Conference - Conference Digest, DRC, pp. 187-188, 67th Device Research Conference, DRC 2009, University Park, PA, United States, 6/22/09. https://doi.org/10.1109/DRC.2009.5354943

Self-aligned-gate PEALD ZnO TFT circuits. / Mourey, Devin A.; Zhao, Dalong A.; Jackson, Thomas N.

67th Device Research Conference, DRC 2009. 2009. p. 187-188 5354943 (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin film transistors (TFTs) with a self-aligned-gate process to fabricate high speed circuits. Sputter deposited ZnO films have been widely studied, but there have been few reports of dense thin films and high performance devices and circuits. Atomic layer deposition (ALD) of ZnO has been shown to be a very uniform and conformal process, but ALD ZnO films typically have high background carrier concentration and require doping compensation for enhancement-mode TFTs. PEALD provides the uniform conformal coating of ALD and enhancement-mode devices from uncompensated films. Our PEALD ZnO TFTs have linear field-effect mobility >20 cm2/V·s and saturation field-effect mobility >30 cm2/V·s and PEALD ring oscillators with beta ratio ∼5, channel length ∼2.8 μm, and ∼1.5 μm gate-source/drain overlap operate at ∼25 ns/stage. Recently, scaled indium-galliumzinc oxide ring oscillator circuits on silicon substrates (0.5 μm channel length, and 0.5 μm overlap) were reported to operate at ∼7 ns/stage with a saturated-load inverter design, and < 1 ns/stage with a novel bootstrapped inverter design [1]. The speed of our previous PEALD circuits [2] was largely limited by the parasitic capacitance between the gate and drain, and a self-aligned-gate process would provide higher speed devices and circuits. Here we have report a simple self-aligned-gate process for ZnO TFTs and high speed circuits.

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Mourey DA, Zhao DA, Jackson TN. Self-aligned-gate PEALD ZnO TFT circuits. In 67th Device Research Conference, DRC 2009. 2009. p. 187-188. 5354943. (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2009.5354943