Self-aligned-gate ZnO TFT circuits

Devin A. Mourey, Dalong A. Zhao, Thomas Nelson Jackson

Research output: Contribution to journalArticle

32 Scopus citations

Abstract

We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin-film transistors (TFTs) with a gateself-aligned process to fabricate high-speed circuits. The speed of our previous PEALD circuits (22 ns/stage) was largely limited by the parasitic capacitance between the gate and drain, and a self-aligned-gate process provides higher speed devices and circuits. In this letter, a backside exposure process was used to fabricate gate-self-aligned TFTs with a mobility of 20 cm2/V s. The sevenstage self-aligned-gate PEALD ZnO TFT ring oscillators had a propagation delay of 9.8 ns/stage at a supply voltage of 18 V. These ring oscillators are similar in performance to the best reported saturated-load oxide-semiconductor circuits but with much longer channel length (>5×longer).

Original languageEnglish (US)
Article number26
Pages (from-to)326-328
Number of pages3
JournalIEEE Electron Device Letters
Volume31
Issue number4
DOIs
StatePublished - Apr 1 2010

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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