SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.

H. Baratte, D. C. La Tulipe, C. M. Knoedler, T. N. Jackson, D. J. Frank, P. M. Solomon, S. L. Wright

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

The authors have developed cold gate and refractory gate self-aligned process for the GaAs-based SISFET. Using either of these approaches, they have demonstrated 0. 7- mu m gate length devices with near-zero threshold voltage, transconductance of 280 mS/mm at 300 K and 400 mS/mm at 77 K and low gate leakage. They have also fabricated 23-stage ring oscillators which yielded delays of 35 ps/gate and speed-power products of 10 fj/gate at 300 K.

Original languageEnglish (US)
Pages (from-to)444-447
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - Jan 1 1986

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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