SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.

H. Baratte; D. C. La Tulipe; C. M. Knoedler; T. N. Jackson; D. J. Frank; P. M. Solomon; S. L. Wright

doi:10.1109/iedm.1986.191215

SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.

H. Baratte, D. C. La Tulipe, C. M. Knoedler, T. N. Jackson, D. J. Frank, P. M. Solomon, S. L. Wright

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

The authors have developed cold gate and refractory gate self-aligned process for the GaAs-based SISFET. Using either of these approaches, they have demonstrated 0. 7- mu m gate length devices with near-zero threshold voltage, transconductance of 280 mS/mm at 300 K and 400 mS/mm at 77 K and low gate leakage. They have also fabricated 23-stage ring oscillators which yielded delays of 35 ps/gate and speed-power products of 10 fj/gate at 300 K.

Original language	English (US)
Pages (from-to)	444-447
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/iedm.1986.191215
State	Published - Jan 1 1986

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/iedm.1986.191215

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@article{51f26ff023d8435ab02fee961bec27a9,

title = "SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.",

abstract = "The authors have developed cold gate and refractory gate self-aligned process for the GaAs-based SISFET. Using either of these approaches, they have demonstrated 0. 7- mu m gate length devices with near-zero threshold voltage, transconductance of 280 mS/mm at 300 K and 400 mS/mm at 77 K and low gate leakage. They have also fabricated 23-stage ring oscillators which yielded delays of 35 ps/gate and speed-power products of 10 fj/gate at 300 K.",

author = "H. Baratte and {La Tulipe}, {D. C.} and Knoedler, {C. M.} and Jackson, {T. N.} and Frank, {D. J.} and Solomon, {P. M.} and Wright, {S. L.}",

year = "1986",

month = jan,

day = "1",

doi = "10.1109/iedm.1986.191215",

language = "English (US)",

pages = "444--447",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.

AU - Baratte, H.

AU - La Tulipe, D. C.

AU - Knoedler, C. M.

AU - Jackson, T. N.

AU - Frank, D. J.

AU - Solomon, P. M.

AU - Wright, S. L.

PY - 1986/1/1

Y1 - 1986/1/1

N2 - The authors have developed cold gate and refractory gate self-aligned process for the GaAs-based SISFET. Using either of these approaches, they have demonstrated 0. 7- mu m gate length devices with near-zero threshold voltage, transconductance of 280 mS/mm at 300 K and 400 mS/mm at 77 K and low gate leakage. They have also fabricated 23-stage ring oscillators which yielded delays of 35 ps/gate and speed-power products of 10 fj/gate at 300 K.

AB - The authors have developed cold gate and refractory gate self-aligned process for the GaAs-based SISFET. Using either of these approaches, they have demonstrated 0. 7- mu m gate length devices with near-zero threshold voltage, transconductance of 280 mS/mm at 300 K and 400 mS/mm at 77 K and low gate leakage. They have also fabricated 23-stage ring oscillators which yielded delays of 35 ps/gate and speed-power products of 10 fj/gate at 300 K.

UR - http://www.scopus.com/inward/record.url?scp=0023014955&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023014955&partnerID=8YFLogxK

U2 - 10.1109/iedm.1986.191215

DO - 10.1109/iedm.1986.191215

M3 - Conference article

AN - SCOPUS:0023014955

SP - 444

EP - 447

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

ER -

SELF-ALIGNED PROCESSES FOR THE GaAs GATE FET.

Abstract

All Science Journal Classification (ASJC) codes

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