Side channel attacks on STTRAM and low-overhead countermeasures

Anirudh Iyengar, Swaroop Ghosh, Nitin Rathi, Helia Naeimi

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Scopus citations

    Abstract

    Spin-Torque Transfer RAM (STTRAM) is a promising candidate for last level cache due to its high density, high endurance and low leakage. Although promising, STTRAM suffers from high write latency and write current. Additionally, the latency and current depends on the polarity of the data being written. These factors introduce security vulnerabilities and expose the cache memory to side channel attacks (SCA). In this paper we propose a SCA model where the adversary can monitor the supply current of the memory array to partially identify the sensitive cache data that is being read or written. We propose a suite of low-cost solutions such as short retention STTRAM, obfuscation of side channel using 1-bit parity and multi-bit random write, and, neutralizing the side channel using constant current write driver to mitigate the attack. Our analysis reveal that the 1-bit parity reduces the number of distinct write current states by 30% for 32-bit word and the current signature is further obfuscated by multi-bit random writes. Constant current write makes it more challenging for the attacker to extract the entire word using a single supply current signature.

    Original languageEnglish (US)
    Title of host publication2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages141-146
    Number of pages6
    ISBN (Electronic)9781509036233
    DOIs
    StatePublished - Oct 25 2016
    Event29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016 - Storrs, United States
    Duration: Sep 19 2016Sep 20 2016

    Publication series

    Name2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016

    Other

    Other29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
    Country/TerritoryUnited States
    CityStorrs
    Period9/19/169/20/16

    All Science Journal Classification (ASJC) codes

    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality
    • Hardware and Architecture

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