Silicon nanowire tunneling field-effect transistor arrays: Improving subthreshold performance using excimer laser annealing

Joshua T. Smith, Christian Sandow, Saptarshi Das, Renato A. Minamisawa, Siegfried Mantl, Joerg Appenzeller

Research output: Contribution to journalArticlepeer-review

40 Scopus citations

Abstract

We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.

Original languageEnglish (US)
Article number5766728
Pages (from-to)1822-1829
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume58
Issue number7
DOIs
StatePublished - Jul 1 2011

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Silicon nanowire tunneling field-effect transistor arrays: Improving subthreshold performance using excimer laser annealing'. Together they form a unique fingerprint.

Cite this