Simulating DRAM controllers for future system architecture exploration

Andreas Hansson, Neha Agarwal, Aasheesh Kolli, Thomas Wenisch, Aniruddha N. Udipi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Citations (Scopus)

Abstract

Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power, and it is key to capture the complex behaviour of the DRAM controller when evaluating CPU and GPU performance. By using full-system simulation, the interactions between the system components is captured. However, traditional DRAM controller models focus on modelling interactions between the controller and the DRAM rather than the interactions with the system. Moreover, the DRAM interactions are modelled on a cycle-by-cycle basis, leading to inflexibility and poor simulation performance. In this work, we present a high-level memory controller model, specifically designed for full-system exploration of future system architectures. Our event-based model is tailored to match a contemporary controller architecture, and captures the most important DRAM timing constraints for current and emerging DRAM interfaces, e.g. DDR3, LPDDR3 and WideIO. We show how our controller leverages the open-source gem5 simulation framework, and compare it to a state-of-the-art DRAM controller simulator. Our results show that our model is 7x faster on average, while maintaining the fidelity of the simulation. To highlight the capabilities of our model, we show that it can be used to evaluate a multi-processor memory system.

Original languageEnglish (US)
Title of host publicationISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software
PublisherIEEE Computer Society
Pages201-210
Number of pages10
ISBN (Print)9781479936052
DOIs
StatePublished - Jan 1 2014
Event2014 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2014 - Monterey, CA, United States
Duration: Mar 23 2014Mar 25 2014

Publication series

NameISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software

Other

Other2014 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2014
CountryUnited States
CityMonterey, CA
Period3/23/143/25/14

Fingerprint

Dynamic random access storage
Controllers
Data storage equipment
Parallel architectures
Mobile devices
Program processors
Computer systems
Servers
Simulators
Bandwidth

All Science Journal Classification (ASJC) codes

  • Software

Cite this

Hansson, A., Agarwal, N., Kolli, A., Wenisch, T., & Udipi, A. N. (2014). Simulating DRAM controllers for future system architecture exploration. In ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software (pp. 201-210). [6844484] (ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software). IEEE Computer Society. https://doi.org/10.1109/ISPASS.2014.6844484
Hansson, Andreas ; Agarwal, Neha ; Kolli, Aasheesh ; Wenisch, Thomas ; Udipi, Aniruddha N. / Simulating DRAM controllers for future system architecture exploration. ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software. IEEE Computer Society, 2014. pp. 201-210 (ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software).
@inproceedings{458550a6ed284df49a6b14b1e30e92fe,
title = "Simulating DRAM controllers for future system architecture exploration",
abstract = "Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power, and it is key to capture the complex behaviour of the DRAM controller when evaluating CPU and GPU performance. By using full-system simulation, the interactions between the system components is captured. However, traditional DRAM controller models focus on modelling interactions between the controller and the DRAM rather than the interactions with the system. Moreover, the DRAM interactions are modelled on a cycle-by-cycle basis, leading to inflexibility and poor simulation performance. In this work, we present a high-level memory controller model, specifically designed for full-system exploration of future system architectures. Our event-based model is tailored to match a contemporary controller architecture, and captures the most important DRAM timing constraints for current and emerging DRAM interfaces, e.g. DDR3, LPDDR3 and WideIO. We show how our controller leverages the open-source gem5 simulation framework, and compare it to a state-of-the-art DRAM controller simulator. Our results show that our model is 7x faster on average, while maintaining the fidelity of the simulation. To highlight the capabilities of our model, we show that it can be used to evaluate a multi-processor memory system.",
author = "Andreas Hansson and Neha Agarwal and Aasheesh Kolli and Thomas Wenisch and Udipi, {Aniruddha N.}",
year = "2014",
month = "1",
day = "1",
doi = "10.1109/ISPASS.2014.6844484",
language = "English (US)",
isbn = "9781479936052",
series = "ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software",
publisher = "IEEE Computer Society",
pages = "201--210",
booktitle = "ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software",
address = "United States",

}

Hansson, A, Agarwal, N, Kolli, A, Wenisch, T & Udipi, AN 2014, Simulating DRAM controllers for future system architecture exploration. in ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software., 6844484, ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software, IEEE Computer Society, pp. 201-210, 2014 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2014, Monterey, CA, United States, 3/23/14. https://doi.org/10.1109/ISPASS.2014.6844484

Simulating DRAM controllers for future system architecture exploration. / Hansson, Andreas; Agarwal, Neha; Kolli, Aasheesh; Wenisch, Thomas; Udipi, Aniruddha N.

ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software. IEEE Computer Society, 2014. p. 201-210 6844484 (ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Simulating DRAM controllers for future system architecture exploration

AU - Hansson, Andreas

AU - Agarwal, Neha

AU - Kolli, Aasheesh

AU - Wenisch, Thomas

AU - Udipi, Aniruddha N.

PY - 2014/1/1

Y1 - 2014/1/1

N2 - Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power, and it is key to capture the complex behaviour of the DRAM controller when evaluating CPU and GPU performance. By using full-system simulation, the interactions between the system components is captured. However, traditional DRAM controller models focus on modelling interactions between the controller and the DRAM rather than the interactions with the system. Moreover, the DRAM interactions are modelled on a cycle-by-cycle basis, leading to inflexibility and poor simulation performance. In this work, we present a high-level memory controller model, specifically designed for full-system exploration of future system architectures. Our event-based model is tailored to match a contemporary controller architecture, and captures the most important DRAM timing constraints for current and emerging DRAM interfaces, e.g. DDR3, LPDDR3 and WideIO. We show how our controller leverages the open-source gem5 simulation framework, and compare it to a state-of-the-art DRAM controller simulator. Our results show that our model is 7x faster on average, while maintaining the fidelity of the simulation. To highlight the capabilities of our model, we show that it can be used to evaluate a multi-processor memory system.

AB - Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power, and it is key to capture the complex behaviour of the DRAM controller when evaluating CPU and GPU performance. By using full-system simulation, the interactions between the system components is captured. However, traditional DRAM controller models focus on modelling interactions between the controller and the DRAM rather than the interactions with the system. Moreover, the DRAM interactions are modelled on a cycle-by-cycle basis, leading to inflexibility and poor simulation performance. In this work, we present a high-level memory controller model, specifically designed for full-system exploration of future system architectures. Our event-based model is tailored to match a contemporary controller architecture, and captures the most important DRAM timing constraints for current and emerging DRAM interfaces, e.g. DDR3, LPDDR3 and WideIO. We show how our controller leverages the open-source gem5 simulation framework, and compare it to a state-of-the-art DRAM controller simulator. Our results show that our model is 7x faster on average, while maintaining the fidelity of the simulation. To highlight the capabilities of our model, we show that it can be used to evaluate a multi-processor memory system.

UR - http://www.scopus.com/inward/record.url?scp=84904463737&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84904463737&partnerID=8YFLogxK

U2 - 10.1109/ISPASS.2014.6844484

DO - 10.1109/ISPASS.2014.6844484

M3 - Conference contribution

SN - 9781479936052

T3 - ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software

SP - 201

EP - 210

BT - ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software

PB - IEEE Computer Society

ER -

Hansson A, Agarwal N, Kolli A, Wenisch T, Udipi AN. Simulating DRAM controllers for future system architecture exploration. In ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software. IEEE Computer Society. 2014. p. 201-210. 6844484. (ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software). https://doi.org/10.1109/ISPASS.2014.6844484