Simulation methodology for software energy evaluation

H. Mehta, R. M. Owens, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We describe a comprehensive simulation methodology and tool for evaluation of software energy for the pipelined DLX processor. Energy models for each module of DLX are built and the energy is evaluated during run time execution. The input to the simulator are the instructions of the program and the simulator estimates energy of each micro-instruction using the energy models. Our simulator allows exploration of energy by allowing architecture modification, experimentation with different software techniques (compilation optimizations, algorithm evaluation) and also allows simultaneous interplay of both hardware and software techniques. The usefulness of this simulator is demonstrated by evaluating certain compilation optimizations (loop unrolling, software pipelining, recursion elimination etc.) and algorithms.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE
Pages509-510
Number of pages2
StatePublished - 1997
EventProceedings of the 1997 10th International Conference on VLSI Design - Hyderabad, India
Duration: Jan 4 1997Jan 7 1997

Other

OtherProceedings of the 1997 10th International Conference on VLSI Design
CityHyderabad, India
Period1/4/971/7/97

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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