Simultaneous memory and bus partitioning for SoC architectures

Suresh Srinivasan, Federico Angiolini, Martino Ruggiero, Luca Benini, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

There has been a continued proliferation in the demand for application specific System on Chip Cores in the recent years. Meeting the power budget constraint continues to be a major challenge for the designers architecting such systems. In this work, we demonstrate that simultaneous partitioning of the bus and memory subsystem into smaller segments can be an effective mechanism for reducing the energy consumption of a SoC. We present a genetic algorithm based search mechanism to determine a system configuration that is energy-efficient and validate the effectiveness of the configuration using a cycle-accurate virtual platform for a multiprocessor SoC. Our results using various applications show that the proposed approach gives significant energy savings and accentuates the benefits of previously proposed bus and memory partitioning schemes applied individually or in combination.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, 2005 SOCC
EditorsD. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages125-128
Number of pages4
StatePublished - Dec 1 2005
Event2005 IEEE International SOC Conference - Herndon, VA, United States
Duration: Sep 25 2005Sep 28 2005

Publication series

NameProceedings - IEEE International SOC Conference

Other

Other2005 IEEE International SOC Conference
CountryUnited States
CityHerndon, VA
Period9/25/059/28/05

Fingerprint

Data storage equipment
Energy conservation
Energy utilization
Genetic algorithms
System-on-chip

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Srinivasan, S., Angiolini, F., Ruggiero, M., Benini, L., & Narayanan, V. (2005). Simultaneous memory and bus partitioning for SoC architectures. In D. Ha, R. Krishnamurthy, S. Kim, & A. Marshall (Eds.), Proceedings - IEEE International SOC Conference, 2005 SOCC (pp. 125-128). [TA1.2] (Proceedings - IEEE International SOC Conference).
Srinivasan, Suresh ; Angiolini, Federico ; Ruggiero, Martino ; Benini, Luca ; Narayanan, Vijaykrishnan. / Simultaneous memory and bus partitioning for SoC architectures. Proceedings - IEEE International SOC Conference, 2005 SOCC. editor / D. Ha ; R. Krishnamurthy ; S. Kim ; A. Marshall. 2005. pp. 125-128 (Proceedings - IEEE International SOC Conference).
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Srinivasan, S, Angiolini, F, Ruggiero, M, Benini, L & Narayanan, V 2005, Simultaneous memory and bus partitioning for SoC architectures. in D Ha, R Krishnamurthy, S Kim & A Marshall (eds), Proceedings - IEEE International SOC Conference, 2005 SOCC., TA1.2, Proceedings - IEEE International SOC Conference, pp. 125-128, 2005 IEEE International SOC Conference, Herndon, VA, United States, 9/25/05.

Simultaneous memory and bus partitioning for SoC architectures. / Srinivasan, Suresh; Angiolini, Federico; Ruggiero, Martino; Benini, Luca; Narayanan, Vijaykrishnan.

Proceedings - IEEE International SOC Conference, 2005 SOCC. ed. / D. Ha; R. Krishnamurthy; S. Kim; A. Marshall. 2005. p. 125-128 TA1.2 (Proceedings - IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - There has been a continued proliferation in the demand for application specific System on Chip Cores in the recent years. Meeting the power budget constraint continues to be a major challenge for the designers architecting such systems. In this work, we demonstrate that simultaneous partitioning of the bus and memory subsystem into smaller segments can be an effective mechanism for reducing the energy consumption of a SoC. We present a genetic algorithm based search mechanism to determine a system configuration that is energy-efficient and validate the effectiveness of the configuration using a cycle-accurate virtual platform for a multiprocessor SoC. Our results using various applications show that the proposed approach gives significant energy savings and accentuates the benefits of previously proposed bus and memory partitioning schemes applied individually or in combination.

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Srinivasan S, Angiolini F, Ruggiero M, Benini L, Narayanan V. Simultaneous memory and bus partitioning for SoC architectures. In Ha D, Krishnamurthy R, Kim S, Marshall A, editors, Proceedings - IEEE International SOC Conference, 2005 SOCC. 2005. p. 125-128. TA1.2. (Proceedings - IEEE International SOC Conference).