Simultaneous partitioning and frequency assignment for on-chip bus architectures

Suresh Srinivasan, Lin Li, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Pages218-223
Number of pages6
DOIs
Publication statusPublished - Dec 1 2005
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
VolumeI
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Srinivasan, S., Li, L., & Vijaykrishnan, N. (2005). Simultaneous partitioning and frequency assignment for on-chip bus architectures. In Proceedings - Design, Automation and Test in Europe, DATE '05 (pp. 218-223). [1395559] (Proceedings -Design, Automation and Test in Europe, DATE '05; Vol. I). https://doi.org/10.1109/DATE.2005.269