Simultaneous sizing, reference voltage and clamp voltage biasing for robustness, self-calibration and testability of sttram arrays

Seyedhamidreza Motaman, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the limited sense-margin poses challenge towards applicability of STTRAM. Reference voltage (Vref) biasing and clamp voltage (Vclamp) biasing are possible techniques to balance '0' and '1' sense margins for improved robustness. In this paper, we show that Vref and Vclamp biasing are more effective when employed on appropriately sized sense circuit. Our investigation also reveals that these two techniques can be used for meeting two different objectives namely, self-calibration and improved testability. We show that the proposed sizing and biasing technique can improve both robustness and testability while sacrificing minimum sense margin compared to conventional sense circuit that is designed to provide best sense margin.

Original languageEnglish (US)
Title of host publicationDAC 2014 - 51st Design Automation Conference, Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479930173
DOIs
StatePublished - Jan 1 2014
Event51st Annual Design Automation Conference, DAC 2014 - San Francisco, CA, United States
Duration: Jun 2 2014Jun 5 2014

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other51st Annual Design Automation Conference, DAC 2014
CountryUnited States
CitySan Francisco, CA
Period6/2/146/5/14

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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