Slicing based code parallelization for minimizing inter-processor communication

Mahmut Kandemir, Yuanrui Zhang, Sai Prasanth Muralidhara, Ozcan Ozturk, Sri Hari Krishna Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new code parallelization scheme for data-intensive applications. This scheme targets distributed memory multi-core architectures, and formulates the problem of data-computation distribution (partitioning) across parallel processors using slicing such that, starting with the partitioning of the output arrays, it iteratively determines the partitions of other arrays as well as iteration spaces of the loop nests in the application code. The goal is to minimize inter-processor data communications. Based on this iteration space slicing based formulation of the problem, we also propose a solution scheme. The proposed data-computation scheme is evaluated using six data-intensive benchmark programs. In our experimental evaluation, we also compare this scheme against three alternate data-computation distribution schemes. The results obtained are very encouraging, indicating around 10% better speedup, with 16 processors, over the next-best scheme when averaged over all benchmark codes we tested.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09
Pages87-95
Number of pages9
DOIs
StatePublished - Dec 21 2009
EventEmbedded Systems Week 2009, ESWEEK 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09 - Grenoble, France
Duration: Oct 11 2009Oct 16 2009

Publication series

NameEmbedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09

Other

OtherEmbedded Systems Week 2009, ESWEEK 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09
CountryFrance
CityGrenoble
Period10/11/0910/16/09

Fingerprint

Communication
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Kandemir, M., Zhang, Y., Muralidhara, S. P., Ozturk, O., & Narayanan, S. H. K. (2009). Slicing based code parallelization for minimizing inter-processor communication. In Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09 (pp. 87-95). (Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09). https://doi.org/10.1145/1629395.1629409
Kandemir, Mahmut ; Zhang, Yuanrui ; Muralidhara, Sai Prasanth ; Ozturk, Ozcan ; Narayanan, Sri Hari Krishna. / Slicing based code parallelization for minimizing inter-processor communication. Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09. 2009. pp. 87-95 (Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09).
@inproceedings{698398b712534f6dab6d1d56bed32741,
title = "Slicing based code parallelization for minimizing inter-processor communication",
abstract = "One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new code parallelization scheme for data-intensive applications. This scheme targets distributed memory multi-core architectures, and formulates the problem of data-computation distribution (partitioning) across parallel processors using slicing such that, starting with the partitioning of the output arrays, it iteratively determines the partitions of other arrays as well as iteration spaces of the loop nests in the application code. The goal is to minimize inter-processor data communications. Based on this iteration space slicing based formulation of the problem, we also propose a solution scheme. The proposed data-computation scheme is evaluated using six data-intensive benchmark programs. In our experimental evaluation, we also compare this scheme against three alternate data-computation distribution schemes. The results obtained are very encouraging, indicating around 10{\%} better speedup, with 16 processors, over the next-best scheme when averaged over all benchmark codes we tested.",
author = "Mahmut Kandemir and Yuanrui Zhang and Muralidhara, {Sai Prasanth} and Ozcan Ozturk and Narayanan, {Sri Hari Krishna}",
year = "2009",
month = "12",
day = "21",
doi = "10.1145/1629395.1629409",
language = "English (US)",
isbn = "9781605586267",
series = "Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09",
pages = "87--95",
booktitle = "Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09",

}

Kandemir, M, Zhang, Y, Muralidhara, SP, Ozturk, O & Narayanan, SHK 2009, Slicing based code parallelization for minimizing inter-processor communication. in Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09. Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09, pp. 87-95, Embedded Systems Week 2009, ESWEEK 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09, Grenoble, France, 10/11/09. https://doi.org/10.1145/1629395.1629409

Slicing based code parallelization for minimizing inter-processor communication. / Kandemir, Mahmut; Zhang, Yuanrui; Muralidhara, Sai Prasanth; Ozturk, Ozcan; Narayanan, Sri Hari Krishna.

Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09. 2009. p. 87-95 (Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Slicing based code parallelization for minimizing inter-processor communication

AU - Kandemir, Mahmut

AU - Zhang, Yuanrui

AU - Muralidhara, Sai Prasanth

AU - Ozturk, Ozcan

AU - Narayanan, Sri Hari Krishna

PY - 2009/12/21

Y1 - 2009/12/21

N2 - One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new code parallelization scheme for data-intensive applications. This scheme targets distributed memory multi-core architectures, and formulates the problem of data-computation distribution (partitioning) across parallel processors using slicing such that, starting with the partitioning of the output arrays, it iteratively determines the partitions of other arrays as well as iteration spaces of the loop nests in the application code. The goal is to minimize inter-processor data communications. Based on this iteration space slicing based formulation of the problem, we also propose a solution scheme. The proposed data-computation scheme is evaluated using six data-intensive benchmark programs. In our experimental evaluation, we also compare this scheme against three alternate data-computation distribution schemes. The results obtained are very encouraging, indicating around 10% better speedup, with 16 processors, over the next-best scheme when averaged over all benchmark codes we tested.

AB - One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new code parallelization scheme for data-intensive applications. This scheme targets distributed memory multi-core architectures, and formulates the problem of data-computation distribution (partitioning) across parallel processors using slicing such that, starting with the partitioning of the output arrays, it iteratively determines the partitions of other arrays as well as iteration spaces of the loop nests in the application code. The goal is to minimize inter-processor data communications. Based on this iteration space slicing based formulation of the problem, we also propose a solution scheme. The proposed data-computation scheme is evaluated using six data-intensive benchmark programs. In our experimental evaluation, we also compare this scheme against three alternate data-computation distribution schemes. The results obtained are very encouraging, indicating around 10% better speedup, with 16 processors, over the next-best scheme when averaged over all benchmark codes we tested.

UR - http://www.scopus.com/inward/record.url?scp=72049109210&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=72049109210&partnerID=8YFLogxK

U2 - 10.1145/1629395.1629409

DO - 10.1145/1629395.1629409

M3 - Conference contribution

SN - 9781605586267

T3 - Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09

SP - 87

EP - 95

BT - Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09

ER -

Kandemir M, Zhang Y, Muralidhara SP, Ozturk O, Narayanan SHK. Slicing based code parallelization for minimizing inter-processor communication. In Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09. 2009. p. 87-95. (Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09). https://doi.org/10.1145/1629395.1629409