TY - GEN
T1 - Soft error and energy consumption interactions
T2 - Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
AU - Li, Lin
AU - Degalahal, Vijay
AU - Vijaykrishnan, N.
AU - Kandemir, Mahmut
AU - Irwin, Mary Jane
PY - 2004
Y1 - 2004
N2 - Energy-efficiency and reliability are two major design constraints influencing next generation system designs. In this work, we focus on the interaction between power consumption and reliability considering the on-chip data caches. First, we investigate the impact of two commonly used architectural-level leakage reduction approaches on the data reliability. Our results indicate that the leakage optimization techniques can have very different reliability behavior as compared to an original cache with no leakage optimizations. Next, we investigate on providing data reliability in an energy-efficient fashion in the presence of soft-errors. In contrast to current commercial caches that treat and protect all data using the same error detection/correction mechanism, we present an adaptive error coding scheme that treats dirty and clean data cache blocks differently. Furthermore, we present an early-write-back scheme that enhances the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability. Experimental results show that proposed schemes, when used in conjunction, can reduce dynamic energy of error protection components in L1 data cache by 11% on average without impacting the performance or reliability.
AB - Energy-efficiency and reliability are two major design constraints influencing next generation system designs. In this work, we focus on the interaction between power consumption and reliability considering the on-chip data caches. First, we investigate the impact of two commonly used architectural-level leakage reduction approaches on the data reliability. Our results indicate that the leakage optimization techniques can have very different reliability behavior as compared to an original cache with no leakage optimizations. Next, we investigate on providing data reliability in an energy-efficient fashion in the presence of soft-errors. In contrast to current commercial caches that treat and protect all data using the same error detection/correction mechanism, we present an adaptive error coding scheme that treats dirty and clean data cache blocks differently. Furthermore, we present an early-write-back scheme that enhances the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability. Experimental results show that proposed schemes, when used in conjunction, can reduce dynamic energy of error protection components in L1 data cache by 11% on average without impacting the performance or reliability.
UR - http://www.scopus.com/inward/record.url?scp=16244375550&partnerID=8YFLogxK
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M3 - Conference contribution
AN - SCOPUS:16244375550
SN - 1581139292
T3 - Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
SP - 132
EP - 137
BT - Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
Y2 - 9 August 2004 through 11 August 2004
ER -