Abstract
Gray code addressing is one of the techniques previously proposed to reduce switching activity on high capacitance address bus lines. However in order to convert a system to gray address encoding there are several issues a designer needs to consider. This paper analyzes two issues which include gray code encodings for counter increments other than one and tradeoffs in power consumption incurred due to code conversions (binary to gray, gray to binary) when considering address increments and adders. Results are shown for different encodings and different configurations.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 178-181 |
| Number of pages | 4 |
| Journal | Proceedings of the IEEE Great Lakes Symposium on VLSI |
| State | Published - 1996 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering