Spacer thickness optimization for FinFET-based logic and memories

A device- circuit co-design approach

Sumeet Kumar Gupta, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We present device-circuit co-design techniques for FinFETs, based on spacer thickness optimization. We show that short channel effects in deeply scaled technologies can be mitigated by engineering the spacer thickness to introduce a gate underlap. FinFETs with symmetric and asymmetric gate underlap are presented and their device characteristics are analyzed. The implication of introducing underlap in FinFETs on circuit design is also discussed. We show that spacer thickness optimization leads to 86% lower leakage and 14% lower dynamic energy consumption with comparable performance. We also present the benefits of FinFETs with asymmetric gate underlap in mitigating the read-write conflict in 6T SRAMs. This technique enhances the read stability by 10% with only 3% lower write margin compared to standard FinFET SRAM. In addition, 58% reduction in leakage, 3% lower write time and 3% higher hold stability is achieved at the cost of 19% higher access time and 4% larger area.

Original languageEnglish (US)
Title of host publicationDielectric Materials and Metals for Nanoelectronics and Photonics 10
Pages187-192
Number of pages6
Volume50
Edition4
DOIs
StatePublished - Dec 1 2012
EventSymposium on Dielectric Materials and Metals for Nanoelectronics and Photonics - 10 - 222nd ECS Meeting - Honolulu, HI, United States
Duration: Oct 7 2012Oct 12 2012

Other

OtherSymposium on Dielectric Materials and Metals for Nanoelectronics and Photonics - 10 - 222nd ECS Meeting
CountryUnited States
CityHonolulu, HI
Period10/7/1210/12/12

Fingerprint

Data storage equipment
Networks (circuits)
Static random access storage
Energy utilization
FinFET

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Gupta, S. K., & Roy, K. (2012). Spacer thickness optimization for FinFET-based logic and memories: A device- circuit co-design approach. In Dielectric Materials and Metals for Nanoelectronics and Photonics 10 (4 ed., Vol. 50, pp. 187-192) https://doi.org/10.1149/05004.0187ecst
Gupta, Sumeet Kumar ; Roy, Kaushik. / Spacer thickness optimization for FinFET-based logic and memories : A device- circuit co-design approach. Dielectric Materials and Metals for Nanoelectronics and Photonics 10. Vol. 50 4. ed. 2012. pp. 187-192
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Gupta, SK & Roy, K 2012, Spacer thickness optimization for FinFET-based logic and memories: A device- circuit co-design approach. in Dielectric Materials and Metals for Nanoelectronics and Photonics 10. 4 edn, vol. 50, pp. 187-192, Symposium on Dielectric Materials and Metals for Nanoelectronics and Photonics - 10 - 222nd ECS Meeting, Honolulu, HI, United States, 10/7/12. https://doi.org/10.1149/05004.0187ecst

Spacer thickness optimization for FinFET-based logic and memories : A device- circuit co-design approach. / Gupta, Sumeet Kumar; Roy, Kaushik.

Dielectric Materials and Metals for Nanoelectronics and Photonics 10. Vol. 50 4. ed. 2012. p. 187-192.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Gupta SK, Roy K. Spacer thickness optimization for FinFET-based logic and memories: A device- circuit co-design approach. In Dielectric Materials and Metals for Nanoelectronics and Photonics 10. 4 ed. Vol. 50. 2012. p. 187-192 https://doi.org/10.1149/05004.0187ecst