The authors report on the implementation of a path planning algorithm on the TrueNorth neurosynaptic system. Their implementation exploits processing in the temporal domain within the architectural constraints of the TrueNorth chip to deduce the optimal path. The optimal path is computed on the TrueNorth chip for grid maps with dimensions as large as 173 × 168 nodes consuming ∼70 mW at an operating voltage of 0.8 V.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering