Spin dependent trapping in a polycrystalline silicon integrated circuit resistor

Spin dependent trapping of majority carriers at trivalent silicon centers in the grain boundaries of a polycrystalline silicon integrated circuit resistor has been observed. The phenomenon has been studied both in a silicon bicrystal and in thin-film polycrystalline silicon with essentially identical results. This not only identifies the trapping center responsible for the large barriers observed at silicon grain boundaries, but also demonstrates that the technique has the sensitivity required to work with actual microelectronic devices.