Sprinkler: Maximizing resource utilization in many-chip solid state disks

Myoungsoo Jung, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource utilization and achieving high performance without additional NAND flash chips. Specifically, Sprinkler relaxes parallelism dependency by scheduling I/O requests based on internal resource layout rather than the order imposed by the device-level queue. In addition, Sprinkler improves flash-level parallelism and reduces the number of transactions (i.e., improves transactionallocality) by over-committing flash memory requests to specific resources. Our extensive experimental evaluation using a cycle-accurate large-scale SSD simulation framework shows that a many-chip SSD equipped with our Sprinkler provides at least 56.6% shorter latency and 1.8 -2.2 times better throughput than the state-of-the-art SSD controllers. Further, it improves overall resource utilization by 68.8% under different I/O request patterns and provides, on average, 80.2% more flash-level parallelism by reducing half of the flash memory requests at runtime.

Original languageEnglish (US)
Title of host publication20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
PublisherIEEE Computer Society
Pages524-535
Number of pages12
ISBN (Print)9781479930975
DOIs
StatePublished - Jan 1 2014
Event20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 - Orlando, FL, United States
Duration: Feb 15 2014Feb 19 2014

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014
CountryUnited States
CityOrlando, FL
Period2/15/142/19/14

Fingerprint

Flash memory
Controllers
Scheduling
Throughput

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Jung, M., & Kandemir, M. (2014). Sprinkler: Maximizing resource utilization in many-chip solid state disks. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014 (pp. 524-535). [6835961] (Proceedings - International Symposium on High-Performance Computer Architecture). IEEE Computer Society. https://doi.org/10.1109/HPCA.2014.6835961
Jung, Myoungsoo ; Kandemir, Mahmut. / Sprinkler : Maximizing resource utilization in many-chip solid state disks. 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014. IEEE Computer Society, 2014. pp. 524-535 (Proceedings - International Symposium on High-Performance Computer Architecture).
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Jung, M & Kandemir, M 2014, Sprinkler: Maximizing resource utilization in many-chip solid state disks. in 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014., 6835961, Proceedings - International Symposium on High-Performance Computer Architecture, IEEE Computer Society, pp. 524-535, 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, United States, 2/15/14. https://doi.org/10.1109/HPCA.2014.6835961

Sprinkler : Maximizing resource utilization in many-chip solid state disks. / Jung, Myoungsoo; Kandemir, Mahmut.

20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014. IEEE Computer Society, 2014. p. 524-535 6835961 (Proceedings - International Symposium on High-Performance Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jung M, Kandemir M. Sprinkler: Maximizing resource utilization in many-chip solid state disks. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014. IEEE Computer Society. 2014. p. 524-535. 6835961. (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2014.6835961