Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

Melvin Eze, Ozcan Ozturk, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.

Original languageEnglish (US)
Title of host publication2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
PublisherIEEE Computer Society
Pages296-301
Number of pages6
ISBN (Print)9781479905249
DOIs
StatePublished - Jan 1 2013
Event2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, Turkey
Duration: Oct 7 2013Oct 9 2013

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Other

Other2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
CountryTurkey
CityIstanbul
Period10/7/1310/9/13

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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  • Cite this

    Eze, M., Ozturk, O., & Narayanan, V. (2013). Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings (pp. 296-301). [6673296] (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2013.6673296