We give an overview of the QPACE project, which is pursuing the development of a massively parallel, scalable supercomputer for LQCD. The machine is a three-dimensional torus of identical processing nodes, based on the PowerXCell 8i processor. The nodes are connected by an FPGA-based, application-optimized network processor attached to the PowerXCell 8i processor. We present a performance analysis of lattice QCD codes on QPACE and corresponding hardware benchmarks.
|Original language||English (US)|
|Journal||Proceedings of Science|
|State||Published - 2008|
|Event||26th International Symposium on Lattice Field Theory, LATTICE 2008 - Williamsburg, United States|
Duration: Jul 14 2008 → Jul 19 2008
All Science Journal Classification (ASJC) codes