Hyper-FET, an emerging device with unconventional characteristics, exhibits sub-kT/q switching and can attain higher ON current (ION) than standard FinFETs with matched OFF current (IOFF). In continuation to the insights on the device level design methodology conveyed in part I , here we analyze the circuit implications of the unique characteristics of Hyper-FETs, such as hysteresis and abrupt switching. We provide a comprehensive discussion on the design of Hyper-FET-based circuit primitives, such as inverter, NOR and NAND gates. We emphasize on tailoring the hysteresis to avoid functional failure in logic circuits and deduce the correspondence between hysteresis observed in the device and circuit characteristics. To complement the device level constraints presented in part I, here we present additional stringencies for material parameters to aid in designing Hyper-FET-based logic gates with regenerative property and rail-to-railswing. Our analysis indicates that, at low VDD (<0.3 V), properly designed Hyper-FET-based inverters can exhibit 25%-68% less energy at iso-delay (compared with FinFET-based CMOS inverters). We also provide targets for future material exploration.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering