Abstract
It is well known that reducing gate length is a powerful means to increase the transconductance and transit frequency of GaAs MESFET devices. However, by reducing the gate length without scaling channel doping and thickness, the performance obtained is limited by short-channel effects and parasitics. In this paper we present an overview of our work on two different MESFET structures, illustrating how device performance can be increased by decreasing the gate length, with the result that appropriately scaled MESFETs compare favorably with GaAs-AlGaAs heterojunction FETs. From our work - including some recent results on 0.15-μm-gate-length implantation-self-aligned MESFETs - we conclude that it should be possible to increase the speed of high-speed GaAs MESFET (logic, analog, and microwave) circuits through the use of devices having gate lengths less than 0.5 μm.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 495-505 |
| Number of pages | 11 |
| Journal | IBM Journal of Research and Development |
| Volume | 34 |
| Issue number | 4 |
| DOIs | |
| State | Published - Jan 1 1990 |
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All Science Journal Classification (ASJC) codes
- Computer Science(all)
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Submicron-gate-length GaAs MESFETs. / Jackson, Thomas Nelson; Van Zeghbroeck, B. J.; Pepper, G.; DeGelormo, J. F.; Keuch, T.; Meier, H.; Wolf, P.
In: IBM Journal of Research and Development, Vol. 34, No. 4, 01.01.1990, p. 495-505.Research output: Contribution to journal › Article
TY - JOUR
T1 - Submicron-gate-length GaAs MESFETs
AU - Jackson, Thomas Nelson
AU - Van Zeghbroeck, B. J.
AU - Pepper, G.
AU - DeGelormo, J. F.
AU - Keuch, T.
AU - Meier, H.
AU - Wolf, P.
PY - 1990/1/1
Y1 - 1990/1/1
N2 - It is well known that reducing gate length is a powerful means to increase the transconductance and transit frequency of GaAs MESFET devices. However, by reducing the gate length without scaling channel doping and thickness, the performance obtained is limited by short-channel effects and parasitics. In this paper we present an overview of our work on two different MESFET structures, illustrating how device performance can be increased by decreasing the gate length, with the result that appropriately scaled MESFETs compare favorably with GaAs-AlGaAs heterojunction FETs. From our work - including some recent results on 0.15-μm-gate-length implantation-self-aligned MESFETs - we conclude that it should be possible to increase the speed of high-speed GaAs MESFET (logic, analog, and microwave) circuits through the use of devices having gate lengths less than 0.5 μm.
AB - It is well known that reducing gate length is a powerful means to increase the transconductance and transit frequency of GaAs MESFET devices. However, by reducing the gate length without scaling channel doping and thickness, the performance obtained is limited by short-channel effects and parasitics. In this paper we present an overview of our work on two different MESFET structures, illustrating how device performance can be increased by decreasing the gate length, with the result that appropriately scaled MESFETs compare favorably with GaAs-AlGaAs heterojunction FETs. From our work - including some recent results on 0.15-μm-gate-length implantation-self-aligned MESFETs - we conclude that it should be possible to increase the speed of high-speed GaAs MESFET (logic, analog, and microwave) circuits through the use of devices having gate lengths less than 0.5 μm.
UR - http://www.scopus.com/inward/record.url?scp=0025455144&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0025455144&partnerID=8YFLogxK
U2 - 10.1147/rd.344.0495
DO - 10.1147/rd.344.0495
M3 - Article
AN - SCOPUS:0025455144
VL - 34
SP - 495
EP - 505
JO - IBM Journal of Research and Development
JF - IBM Journal of Research and Development
SN - 0018-8646
IS - 4
ER -