Supercapacity (>1000 μf/cm 2 ) charge release in a CVD-grown WSe 2 FET incorporating a PEO

CsCIO 4 side gate

M. Asghari Heidarlou, Bhakti Jariwala, P. Paletti, S. Rouvimov, J. A. Robinsorr, S. K. Fullerton-Shirey, A. Seabaugh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We report extraordinarily high capacitance density in tungsten diselenide (WSe 2 ) field-effect transistors (FETs) capped with polyethylene oxide (PEO) and ion doped with cesium perchlorate (CsCIO 4 ). The FETs have 3-4 monolayer WSe 2 channels grown by chemical vapor deposition (CVD) using W(CO) 6 and H2Se at 800 °C for 30 minutes [1]. A stepper-based process was used to fabricate the transistors and an 11 nm Al 2 O 3 atomic layer deposited (ALD) gate dielectric was formed on the WSe 2 with a low temperature nucleation layer, 1 nm Ah03, deposited at 110 °C to facilitate nucleation followed by a 10 nm Ah03 deposited at 200 °C, after Kwak [2]. The n-FET achieves an ON/OFF ratio of 10 6 with noise-floor-limited gate current. Most prior studies of WSe 2 FETs have been on exfoliated materials and to our knowledge there is only one prior report of a top-gated CVD WSe 2 p-FET [3]. Following FET characterization PEO: CsCIO 4 was drop-cast and annealed at 90 °C for 3 minutes in Ar after Xu [4], yielding a layer thickness of 400 nm as measured by transmission electron microscopy (TEM). Ion gating using a side gate (6μm from the WSe 2 mesa edge) produces ambipolar transfer characteristics with approximately equal ON-currents of 2μ A/μm attributed to the multi-work-function source/drain contacts [5]. ON/OFF current ratio exceeds 10 6 with field-effect electron and hole mobilities of 10 and 25 cm 2 /Vs respectively and subthreshold swings of 260 and 180 mY/decade respectively. Atomic force microscope images show that the WSe 2 nucleates in triangles which are apparent in Fig. 1; FET characteristics after testing of the transistor are shown in Fig. 2 along with TEM.

Original languageEnglish (US)
Title of host publication2018 76th Device Research Conference, DRC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781538630280
DOIs
StatePublished - Aug 20 2018
Event76th Device Research Conference, DRC 2018 - Santa Barbara, United States
Duration: Jun 24 2018Jun 27 2018

Publication series

NameDevice Research Conference - Conference Digest, DRC
Volume2018-June
ISSN (Print)1548-3770

Other

Other76th Device Research Conference, DRC 2018
CountryUnited States
CitySanta Barbara
Period6/24/186/27/18

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Field effect transistors
Polyethylene oxides
Chemical vapor deposition
Transistors
Nucleation
Transmission electron microscopy
Hole mobility
Electron mobility
Gate dielectrics
Ions
Cesium
Tungsten
Monolayers
Microscopes
Capacitance
Testing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Heidarlou, M. A., Jariwala, B., Paletti, P., Rouvimov, S., Robinsorr, J. A., Fullerton-Shirey, S. K., & Seabaugh, A. (2018). Supercapacity (>1000 μf/cm 2 ) charge release in a CVD-grown WSe 2 FET incorporating a PEO: CsCIO 4 side gate. In 2018 76th Device Research Conference, DRC 2018 [8442277] (Device Research Conference - Conference Digest, DRC; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DRC.2018.8442277
Heidarlou, M. Asghari ; Jariwala, Bhakti ; Paletti, P. ; Rouvimov, S. ; Robinsorr, J. A. ; Fullerton-Shirey, S. K. ; Seabaugh, A. / Supercapacity (>1000 μf/cm 2 ) charge release in a CVD-grown WSe 2 FET incorporating a PEO : CsCIO 4 side gate. 2018 76th Device Research Conference, DRC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. (Device Research Conference - Conference Digest, DRC).
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title = "Supercapacity (>1000 μf/cm 2 ) charge release in a CVD-grown WSe 2 FET incorporating a PEO: CsCIO 4 side gate",
abstract = "We report extraordinarily high capacitance density in tungsten diselenide (WSe 2 ) field-effect transistors (FETs) capped with polyethylene oxide (PEO) and ion doped with cesium perchlorate (CsCIO 4 ). The FETs have 3-4 monolayer WSe 2 channels grown by chemical vapor deposition (CVD) using W(CO) 6 and H2Se at 800 °C for 30 minutes [1]. A stepper-based process was used to fabricate the transistors and an 11 nm Al 2 O 3 atomic layer deposited (ALD) gate dielectric was formed on the WSe 2 with a low temperature nucleation layer, 1 nm Ah03, deposited at 110 °C to facilitate nucleation followed by a 10 nm Ah03 deposited at 200 °C, after Kwak [2]. The n-FET achieves an ON/OFF ratio of 10 6 with noise-floor-limited gate current. Most prior studies of WSe 2 FETs have been on exfoliated materials and to our knowledge there is only one prior report of a top-gated CVD WSe 2 p-FET [3]. Following FET characterization PEO: CsCIO 4 was drop-cast and annealed at 90 °C for 3 minutes in Ar after Xu [4], yielding a layer thickness of 400 nm as measured by transmission electron microscopy (TEM). Ion gating using a side gate (6μm from the WSe 2 mesa edge) produces ambipolar transfer characteristics with approximately equal ON-currents of 2μ A/μm attributed to the multi-work-function source/drain contacts [5]. ON/OFF current ratio exceeds 10 6 with field-effect electron and hole mobilities of 10 and 25 cm 2 /Vs respectively and subthreshold swings of 260 and 180 mY/decade respectively. Atomic force microscope images show that the WSe 2 nucleates in triangles which are apparent in Fig. 1; FET characteristics after testing of the transistor are shown in Fig. 2 along with TEM.",
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Heidarlou, MA, Jariwala, B, Paletti, P, Rouvimov, S, Robinsorr, JA, Fullerton-Shirey, SK & Seabaugh, A 2018, Supercapacity (>1000 μf/cm 2 ) charge release in a CVD-grown WSe 2 FET incorporating a PEO: CsCIO 4 side gate. in 2018 76th Device Research Conference, DRC 2018., 8442277, Device Research Conference - Conference Digest, DRC, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., 76th Device Research Conference, DRC 2018, Santa Barbara, United States, 6/24/18. https://doi.org/10.1109/DRC.2018.8442277

Supercapacity (>1000 μf/cm 2 ) charge release in a CVD-grown WSe 2 FET incorporating a PEO : CsCIO 4 side gate. / Heidarlou, M. Asghari; Jariwala, Bhakti; Paletti, P.; Rouvimov, S.; Robinsorr, J. A.; Fullerton-Shirey, S. K.; Seabaugh, A.

2018 76th Device Research Conference, DRC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 8442277 (Device Research Conference - Conference Digest, DRC; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Heidarlou, M. Asghari

AU - Jariwala, Bhakti

AU - Paletti, P.

AU - Rouvimov, S.

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N2 - We report extraordinarily high capacitance density in tungsten diselenide (WSe 2 ) field-effect transistors (FETs) capped with polyethylene oxide (PEO) and ion doped with cesium perchlorate (CsCIO 4 ). The FETs have 3-4 monolayer WSe 2 channels grown by chemical vapor deposition (CVD) using W(CO) 6 and H2Se at 800 °C for 30 minutes [1]. A stepper-based process was used to fabricate the transistors and an 11 nm Al 2 O 3 atomic layer deposited (ALD) gate dielectric was formed on the WSe 2 with a low temperature nucleation layer, 1 nm Ah03, deposited at 110 °C to facilitate nucleation followed by a 10 nm Ah03 deposited at 200 °C, after Kwak [2]. The n-FET achieves an ON/OFF ratio of 10 6 with noise-floor-limited gate current. Most prior studies of WSe 2 FETs have been on exfoliated materials and to our knowledge there is only one prior report of a top-gated CVD WSe 2 p-FET [3]. Following FET characterization PEO: CsCIO 4 was drop-cast and annealed at 90 °C for 3 minutes in Ar after Xu [4], yielding a layer thickness of 400 nm as measured by transmission electron microscopy (TEM). Ion gating using a side gate (6μm from the WSe 2 mesa edge) produces ambipolar transfer characteristics with approximately equal ON-currents of 2μ A/μm attributed to the multi-work-function source/drain contacts [5]. ON/OFF current ratio exceeds 10 6 with field-effect electron and hole mobilities of 10 and 25 cm 2 /Vs respectively and subthreshold swings of 260 and 180 mY/decade respectively. Atomic force microscope images show that the WSe 2 nucleates in triangles which are apparent in Fig. 1; FET characteristics after testing of the transistor are shown in Fig. 2 along with TEM.

AB - We report extraordinarily high capacitance density in tungsten diselenide (WSe 2 ) field-effect transistors (FETs) capped with polyethylene oxide (PEO) and ion doped with cesium perchlorate (CsCIO 4 ). The FETs have 3-4 monolayer WSe 2 channels grown by chemical vapor deposition (CVD) using W(CO) 6 and H2Se at 800 °C for 30 minutes [1]. A stepper-based process was used to fabricate the transistors and an 11 nm Al 2 O 3 atomic layer deposited (ALD) gate dielectric was formed on the WSe 2 with a low temperature nucleation layer, 1 nm Ah03, deposited at 110 °C to facilitate nucleation followed by a 10 nm Ah03 deposited at 200 °C, after Kwak [2]. The n-FET achieves an ON/OFF ratio of 10 6 with noise-floor-limited gate current. Most prior studies of WSe 2 FETs have been on exfoliated materials and to our knowledge there is only one prior report of a top-gated CVD WSe 2 p-FET [3]. Following FET characterization PEO: CsCIO 4 was drop-cast and annealed at 90 °C for 3 minutes in Ar after Xu [4], yielding a layer thickness of 400 nm as measured by transmission electron microscopy (TEM). Ion gating using a side gate (6μm from the WSe 2 mesa edge) produces ambipolar transfer characteristics with approximately equal ON-currents of 2μ A/μm attributed to the multi-work-function source/drain contacts [5]. ON/OFF current ratio exceeds 10 6 with field-effect electron and hole mobilities of 10 and 25 cm 2 /Vs respectively and subthreshold swings of 260 and 180 mY/decade respectively. Atomic force microscope images show that the WSe 2 nucleates in triangles which are apparent in Fig. 1; FET characteristics after testing of the transistor are shown in Fig. 2 along with TEM.

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PB - Institute of Electrical and Electronics Engineers Inc.

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Heidarlou MA, Jariwala B, Paletti P, Rouvimov S, Robinsorr JA, Fullerton-Shirey SK et al. Supercapacity (>1000 μf/cm 2 ) charge release in a CVD-grown WSe 2 FET incorporating a PEO: CsCIO 4 side gate. In 2018 76th Device Research Conference, DRC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. 8442277. (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2018.8442277