Abstract
In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viability of emerging memory technologies based on ferroelectric transistors (FEFETs) for our design. Compared to FEFET memory with standard 1-D access, we achieve 5% energy savings for the proposed memory featuring 2-D read and 93% energy savings for memory with 2-D read and write, for 32 bit column read and write. In addition, we get around 11% and 95% delay savings for 2-D read-enabled memory and 2-D read-write memory, respectively. The application analysis shows that 2-D read-enabled memory achieves around 86% average decrease in row-buffer transactions in 256 × 256 size matrix operations without any array area increase. The 2-D read write memory offers 87% decrease in row-buffer transactions with 28.5% increase in array area compared to the 1-D FEFET memory.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1040-1050 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 26 |
| Issue number | 6 |
| DOIs | |
| State | Published - Jun 1 2018 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
}
Symmetric 2-d-memory access to multidimensional data. / George, Sumitha; Li, Xueqing; Liao, Minli Julie; Ma, Kaisheng; Srinivasa, Srivatsa; Mohan, Karthik; Aziz, Ahmedullah; Sampson, John Morgan; Gupta, Sumeet Kumar; Narayanan, Vijaykrishnan.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 6, 01.06.2018, p. 1040-1050.Research output: Contribution to journal › Article
TY - JOUR
T1 - Symmetric 2-d-memory access to multidimensional data
AU - George, Sumitha
AU - Li, Xueqing
AU - Liao, Minli Julie
AU - Ma, Kaisheng
AU - Srinivasa, Srivatsa
AU - Mohan, Karthik
AU - Aziz, Ahmedullah
AU - Sampson, John Morgan
AU - Gupta, Sumeet Kumar
AU - Narayanan, Vijaykrishnan
PY - 2018/6/1
Y1 - 2018/6/1
N2 - In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viability of emerging memory technologies based on ferroelectric transistors (FEFETs) for our design. Compared to FEFET memory with standard 1-D access, we achieve 5% energy savings for the proposed memory featuring 2-D read and 93% energy savings for memory with 2-D read and write, for 32 bit column read and write. In addition, we get around 11% and 95% delay savings for 2-D read-enabled memory and 2-D read-write memory, respectively. The application analysis shows that 2-D read-enabled memory achieves around 86% average decrease in row-buffer transactions in 256 × 256 size matrix operations without any array area increase. The 2-D read write memory offers 87% decrease in row-buffer transactions with 28.5% increase in array area compared to the 1-D FEFET memory.
AB - In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viability of emerging memory technologies based on ferroelectric transistors (FEFETs) for our design. Compared to FEFET memory with standard 1-D access, we achieve 5% energy savings for the proposed memory featuring 2-D read and 93% energy savings for memory with 2-D read and write, for 32 bit column read and write. In addition, we get around 11% and 95% delay savings for 2-D read-enabled memory and 2-D read-write memory, respectively. The application analysis shows that 2-D read-enabled memory achieves around 86% average decrease in row-buffer transactions in 256 × 256 size matrix operations without any array area increase. The 2-D read write memory offers 87% decrease in row-buffer transactions with 28.5% increase in array area compared to the 1-D FEFET memory.
UR - http://www.scopus.com/inward/record.url?scp=85042703281&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85042703281&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2018.2801302
DO - 10.1109/TVLSI.2018.2801302
M3 - Article
AN - SCOPUS:85042703281
VL - 26
SP - 1040
EP - 1050
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 6
ER -