Software implementations of many symmetric-key encryption algorithms are often inefficient. We study the AES algorithm and its optimised implementations in both software and hardware. Specifically, the performance of AES encryption in processor architectures is considered. Also, we study the performance of optimised AES implementations in Xilinx FPGAs and ASIC devices. We illustrate how modern processors are inadequate when implementing the AES algorithm in terms of performance and power consumption. By comparison, implementations of the AES encryption architectures in FPGAs demonstrate a performance improvement ranging from 50% to approximately 2000%. ASIC implementations are able to achieve even higher performance.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture