Synthesis for Width Minimization in the Single-Electron Transistor Array

Chian Wei Liu, Chang En Chiang, Ching Yi Huang, Yung Chih Chen, Chun Yao Wang, Suman Datta, Vijaykrishnan Narayanan

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

Power consumption has become one of the primary challenges to meetMoore's law. For reducing power consumption, single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow power consumption in operation. Previous works have proposed automated mapping approaches for SET arrays that focused on minimizing the number of hexagons in the SET arrays. However, the area of an SET array is the product of the bounded height and the bounded width, and the height usually equals the number of inputs in the Boolean function. Consequently, in this paper, we focus on the width minimization to reduce the overall area in the mapping of the SET arrays. Our approach consists of techniques of product term minimization, branch-then-share (BTS)-aware variable reordering, SET array architecture relaxation, and BTS-aware product term reordering. The experimental results on a set of MCNC and IWLS 2005 benchmarks show that the proposed approach saves 45% of width compared with the work by Chiang et al., which focused on hexagon count minimization, and also saves 13% of width compared with the work by Chen et al., which focused on width minimization.

Original languageEnglish (US)
Article number7050261
Pages (from-to)2862-2875
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number12
DOIs
StatePublished - Dec 1 2015

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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