System level interconnect power modeling

Yan Zhang, Rita Yu Chen, Wu Ye, Mary Jane Irwin

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

While power consumption of interconnects has become an important issue as technology scales, very few papers on power modeling of interconnects are available in the literature. This paper presents an architectural level interconnect power modeling method and applies it to a commercial chip that integrates a 16-bit DSP and a 32-bit RISC microcontroller. This power modeling method is applicable to any architecture if an architectural level description is provided. An architectural level simulator based on the commercial chip has been enhanced to generate the activity parameters for several signal processing benchmarks and some simple synthetic benchmarks at different technology feature sizes. The power measurements for all six global buses of the chip are reported.

Original languageEnglish (US)
Pages (from-to)289-293
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 1998
EventProceedings of the 1998 11th Annual IEEE International ASIC Conference - Rochester, NY, USA
Duration: Sep 13 1998Sep 16 1998

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Reduced instruction set computing
Microcontrollers
Signal processing
Electric power utilization
Simulators

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Zhang, Yan ; Chen, Rita Yu ; Ye, Wu ; Irwin, Mary Jane. / System level interconnect power modeling. In: Proceedings of the Annual IEEE International ASIC Conference and Exhibit. 1998 ; pp. 289-293.
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System level interconnect power modeling. / Zhang, Yan; Chen, Rita Yu; Ye, Wu; Irwin, Mary Jane.

In: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 01.01.1998, p. 289-293.

Research output: Contribution to journalConference article

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AU - Ye, Wu

AU - Irwin, Mary Jane

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