TaPEr: Tackling power emergencies in the dark silicon era by exploiting resource scalability

Hui Zhao, Mahmut Taylan Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new challenge in multicore design is the management of dark silicon. Among the on-chip components, the cores and caches consume most of the power. We observe that parallel programs exhibit different scalability characteristics with respect to the number of cores and the size of caches. Running programs with fewer cores or smaller caches does not always degrade performance significantly. Based on these observations, we propose a scheme, called TaPEr, that can dynamically (1) predict the scalability of parallel programs with respect to core count and cache capacity; (2) re-allocate available power to cores or caches based on a program's scalability in order to satisfy the power constraints; and (3) achieve high performance (comparing with DVFS or simple shutdown schemes) at the same time.

Original languageEnglish (US)
Title of host publicationProceedings of the 12th ACM International Conference on Computing Frontiers, CF 2015
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450333580
DOIs
StatePublished - May 6 2015
Event12th ACM International Conference on Computing Frontiers, CF 2015 - Ischia, Italy
Duration: May 18 2015May 21 2015

Publication series

NameProceedings of the 12th ACM International Conference on Computing Frontiers, CF 2015

Other

Other12th ACM International Conference on Computing Frontiers, CF 2015
CountryItaly
CityIschia
Period5/18/155/21/15

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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