Targeted random test generation for power-aware multicore designs

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

Research output: Contribution to journalArticle

Abstract

Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test generators play critical roles in pre- and post-silicon validation. The Advanced Configuration and Power Interface (ACPI) standard supports dynamic frequency and voltage scaling by controlling performance states (P-States), yet multicore verification is generally conducted with cores operating at the P0-State. Independently varying core frequencies introduces new sets of intracore and intercore traffic latencies. The article introduces targeted random MP test generation techniques for multicore P-State functional verification. It develops a simple coverage metric to evaluate MP test effectiveness. The metric is demonstrated on MIP's instruction-set-based random MP tests. A novel technique is introduced to modulate the test address space by the spherical Bessel function. The technique delivers an order of magnitude coverage improvement over completely random tests. The article then outlines minimal P-State combinations to be exercised by MP tests. It also formulates two new methodologies to set up and apply MP tests for effective multicore P-State coverage. The methodologies are termed SimInit and SimTransition. First-level analyses indicate that these methods can deliver 97% to 100% improvement over random MP test coverage.

Original languageEnglish (US)
Article number25
JournalACM Transactions on Design Automation of Electronic Systems
Volume17
Issue number3
DOIs
StatePublished - Jun 1 2012

Fingerprint

Data storage equipment
Silicon
Bessel functions
Voltage scaling
Dynamic frequency scaling

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

@article{5160889a6829403194b169de109a674c,
title = "Targeted random test generation for power-aware multicore designs",
abstract = "Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test generators play critical roles in pre- and post-silicon validation. The Advanced Configuration and Power Interface (ACPI) standard supports dynamic frequency and voltage scaling by controlling performance states (P-States), yet multicore verification is generally conducted with cores operating at the P0-State. Independently varying core frequencies introduces new sets of intracore and intercore traffic latencies. The article introduces targeted random MP test generation techniques for multicore P-State functional verification. It develops a simple coverage metric to evaluate MP test effectiveness. The metric is demonstrated on MIP's instruction-set-based random MP tests. A novel technique is introduced to modulate the test address space by the spherical Bessel function. The technique delivers an order of magnitude coverage improvement over completely random tests. The article then outlines minimal P-State combinations to be exercised by MP tests. It also formulates two new methodologies to set up and apply MP tests for effective multicore P-State coverage. The methodologies are termed SimInit and SimTransition. First-level analyses indicate that these methods can deliver 97{\%} to 100{\%} improvement over random MP test coverage.",
author = "Padmaraj Singh and Vijaykrishnan Narayanan and Landis, {David L.}",
year = "2012",
month = "6",
day = "1",
doi = "10.1145/2209291.2209298",
language = "English (US)",
volume = "17",
journal = "ACM Transactions on Design Automation of Electronic Systems",
issn = "1084-4309",
publisher = "Association for Computing Machinery (ACM)",
number = "3",

}

Targeted random test generation for power-aware multicore designs. / Singh, Padmaraj; Narayanan, Vijaykrishnan; Landis, David L.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 17, No. 3, 25, 01.06.2012.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Targeted random test generation for power-aware multicore designs

AU - Singh, Padmaraj

AU - Narayanan, Vijaykrishnan

AU - Landis, David L.

PY - 2012/6/1

Y1 - 2012/6/1

N2 - Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test generators play critical roles in pre- and post-silicon validation. The Advanced Configuration and Power Interface (ACPI) standard supports dynamic frequency and voltage scaling by controlling performance states (P-States), yet multicore verification is generally conducted with cores operating at the P0-State. Independently varying core frequencies introduces new sets of intracore and intercore traffic latencies. The article introduces targeted random MP test generation techniques for multicore P-State functional verification. It develops a simple coverage metric to evaluate MP test effectiveness. The metric is demonstrated on MIP's instruction-set-based random MP tests. A novel technique is introduced to modulate the test address space by the spherical Bessel function. The technique delivers an order of magnitude coverage improvement over completely random tests. The article then outlines minimal P-State combinations to be exercised by MP tests. It also formulates two new methodologies to set up and apply MP tests for effective multicore P-State coverage. The methodologies are termed SimInit and SimTransition. First-level analyses indicate that these methods can deliver 97% to 100% improvement over random MP test coverage.

AB - Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test generators play critical roles in pre- and post-silicon validation. The Advanced Configuration and Power Interface (ACPI) standard supports dynamic frequency and voltage scaling by controlling performance states (P-States), yet multicore verification is generally conducted with cores operating at the P0-State. Independently varying core frequencies introduces new sets of intracore and intercore traffic latencies. The article introduces targeted random MP test generation techniques for multicore P-State functional verification. It develops a simple coverage metric to evaluate MP test effectiveness. The metric is demonstrated on MIP's instruction-set-based random MP tests. A novel technique is introduced to modulate the test address space by the spherical Bessel function. The technique delivers an order of magnitude coverage improvement over completely random tests. The article then outlines minimal P-State combinations to be exercised by MP tests. It also formulates two new methodologies to set up and apply MP tests for effective multicore P-State coverage. The methodologies are termed SimInit and SimTransition. First-level analyses indicate that these methods can deliver 97% to 100% improvement over random MP test coverage.

UR - http://www.scopus.com/inward/record.url?scp=84878512978&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84878512978&partnerID=8YFLogxK

U2 - 10.1145/2209291.2209298

DO - 10.1145/2209291.2209298

M3 - Article

AN - SCOPUS:84878512978

VL - 17

JO - ACM Transactions on Design Automation of Electronic Systems

JF - ACM Transactions on Design Automation of Electronic Systems

SN - 1084-4309

IS - 3

M1 - 25

ER -