Abstract
This chapter reviews several energy-aware design techniques for controlling both active and standby power consumptions that are applicable to MPSoCs. The techniques discussed are for multiprocessor systems-on-chips (MPSoC) processor cores, the on-chip memory hierarchy, the on-chip communication system, and MPSoC energy-aware software. The majority of the techniques are derived from existing uni-processor energy-aware systems that take on new dimensions in the MPSoC space. Techniques for energy and power consumption reduction are successfully applied at all levels of the design space in uni-processor systems-circuit, logic gate, functional unit, processor, system software, and application software levels. The primary focus has been on reducing active power. As technology continues to scale up, accompanied by reductions in the supply and threshold voltages, the percentage of the power budget due to standby energy has driven the development of additional techniques for reducing standby energy.
| Original language | English (US) |
|---|---|
| Title of host publication | Multiprocessor Systems-on-Chips |
| Publisher | Elsevier Inc. |
| Pages | 21-47 |
| Number of pages | 27 |
| ISBN (Print) | 9780123852519 |
| DOIs | |
| State | Published - Dec 1 2005 |
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All Science Journal Classification (ASJC) codes
- Computer Science(all)
Cite this
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Techniques for Designing Energy-Aware MPSoCs. / Irwin, Mary Jane; Benini, Luca; Narayanan, Vijaykrishnan; Kandemir, Mahmut.
Multiprocessor Systems-on-Chips. Elsevier Inc., 2005. p. 21-47.Research output: Chapter in Book/Report/Conference proceeding › Chapter
TY - CHAP
T1 - Techniques for Designing Energy-Aware MPSoCs
AU - Irwin, Mary Jane
AU - Benini, Luca
AU - Narayanan, Vijaykrishnan
AU - Kandemir, Mahmut
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This chapter reviews several energy-aware design techniques for controlling both active and standby power consumptions that are applicable to MPSoCs. The techniques discussed are for multiprocessor systems-on-chips (MPSoC) processor cores, the on-chip memory hierarchy, the on-chip communication system, and MPSoC energy-aware software. The majority of the techniques are derived from existing uni-processor energy-aware systems that take on new dimensions in the MPSoC space. Techniques for energy and power consumption reduction are successfully applied at all levels of the design space in uni-processor systems-circuit, logic gate, functional unit, processor, system software, and application software levels. The primary focus has been on reducing active power. As technology continues to scale up, accompanied by reductions in the supply and threshold voltages, the percentage of the power budget due to standby energy has driven the development of additional techniques for reducing standby energy.
AB - This chapter reviews several energy-aware design techniques for controlling both active and standby power consumptions that are applicable to MPSoCs. The techniques discussed are for multiprocessor systems-on-chips (MPSoC) processor cores, the on-chip memory hierarchy, the on-chip communication system, and MPSoC energy-aware software. The majority of the techniques are derived from existing uni-processor energy-aware systems that take on new dimensions in the MPSoC space. Techniques for energy and power consumption reduction are successfully applied at all levels of the design space in uni-processor systems-circuit, logic gate, functional unit, processor, system software, and application software levels. The primary focus has been on reducing active power. As technology continues to scale up, accompanied by reductions in the supply and threshold voltages, the percentage of the power budget due to standby energy has driven the development of additional techniques for reducing standby energy.
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U2 - 10.1016/B978-012385251-9/50016-5
DO - 10.1016/B978-012385251-9/50016-5
M3 - Chapter
AN - SCOPUS:84882162615
SN - 9780123852519
SP - 21
EP - 47
BT - Multiprocessor Systems-on-Chips
PB - Elsevier Inc.
ER -