Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective

Huichu Liu, Matthew Cotter, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Sea-level soft error performance has been investigated for Si FinFET, III-V FinFET and III-V Heterojunction Tunnel FET in this paper. Transient error generation and transient current profiles in these devices have been evaluated using device simulation. Based on the critical charge extraction for each emerging device-based circuit, the electrical and latching window masking effects have been studied. Below 0.5V, III-V FinFET logic shows reduced soft error rate (SER) compared to Si FinFET. HTFET shows reduced SER for both SRAM and logic compared to Si and III-V FinFET over the evaluated voltage range of 0.3V-0.6V.

Original languageEnglish (US)
Title of host publication2012 IEEE International Electron Devices Meeting, IEDM 2012
DOIs
StatePublished - Dec 1 2012
Event2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States
Duration: Dec 10 2012Dec 13 2012

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2012 IEEE International Electron Devices Meeting, IEDM 2012
CountryUnited States
CitySan Francisco, CA
Period12/10/1212/13/12

Fingerprint

technology assessment
Field effect transistors
tunnels
Tunnels
field effect transistors
logic
masking
sea level
Static random access storage
Sea level
heterojunctions
emerging
Heterojunctions
FinFET
electric potential
profiles
Networks (circuits)
Electric potential
simulation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Liu, H., Cotter, M., Datta, S., & Narayanan, V. (2012). Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective. In 2012 IEEE International Electron Devices Meeting, IEDM 2012 [6479103] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2012.6479103
Liu, Huichu ; Cotter, Matthew ; Datta, Suman ; Narayanan, Vijaykrishnan. / Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective. 2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. (Technical Digest - International Electron Devices Meeting, IEDM).
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Liu, H, Cotter, M, Datta, S & Narayanan, V 2012, Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective. in 2012 IEEE International Electron Devices Meeting, IEDM 2012., 6479103, Technical Digest - International Electron Devices Meeting, IEDM, 2012 IEEE International Electron Devices Meeting, IEDM 2012, San Francisco, CA, United States, 12/10/12. https://doi.org/10.1109/IEDM.2012.6479103

Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective. / Liu, Huichu; Cotter, Matthew; Datta, Suman; Narayanan, Vijaykrishnan.

2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. 6479103 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - Sea-level soft error performance has been investigated for Si FinFET, III-V FinFET and III-V Heterojunction Tunnel FET in this paper. Transient error generation and transient current profiles in these devices have been evaluated using device simulation. Based on the critical charge extraction for each emerging device-based circuit, the electrical and latching window masking effects have been studied. Below 0.5V, III-V FinFET logic shows reduced soft error rate (SER) compared to Si FinFET. HTFET shows reduced SER for both SRAM and logic compared to Si and III-V FinFET over the evaluated voltage range of 0.3V-0.6V.

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Liu H, Cotter M, Datta S, Narayanan V. Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective. In 2012 IEEE International Electron Devices Meeting, IEDM 2012. 2012. 6479103. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2012.6479103