Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads

Nicholas Jao, Srivatsa Srivinasa, Akshay Ramanathan, Minhwan Kim, John Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent advances in emerging technologies such as monolithic 3D Integration (M3D-IC) and emerging non-volatile memory (eNVM) have enabled to embed logic operations in memory. This alleviates the "memory wall" challenges stemming from the time and power expended on migrating data in conventional Von Neumann computing paradigms. We propose a M3D SRAM dot-product engine for compute in-SRAM support used in applications such as matrix multiplication and artificial neural networks. In addition, we propose a novel computing in RRAM-based memory architecture to efficiently solve the computation intensity of sparse dot products. Specifically, the index assessment of sparse matrix-vector multiplication used in support vector machines (SVM). At maximum throughput, our proposed RRAM architecture achieves 11.3× speed up when compared against a near-memory accelerator.

Original languageEnglish (US)
Title of host publicationNANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728155203
DOIs
StatePublished - Jul 2019
Event15th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019 - Qingdao, China
Duration: Jul 17 2019Jul 19 2019

Publication series

NameNANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings

Conference

Conference15th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019
CountryChina
CityQingdao
Period7/17/197/19/19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Signal Processing
  • Electrical and Electronic Engineering

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    Jao, N., Srivinasa, S., Ramanathan, A., Kim, M., Sampson, J., & Narayanan, V. (2019). Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads. In NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings [9073662] (NANOARCH 2019 - 15th IEEE/ACM International Symposium on Nanoscale Architectures, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NANOARCH47378.2019.181303