At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising non-volatile memories (NVMs) are being investigated by the scientific community to address the issue. Some of the NVMs such as Spin-Transfer Torque RAM, Magnetic RAM, Resistive RAM, Phase Change Memory and Ferroelectric RAM have already entered the mainstream computing. However, the unique characteristics of these NVMs bring new fault models such as statistical and stochastic retention failures, magnetic and thermal tolerance failures, voltage droop and ground bounce induced read and write failures and long latency failures. In this work, we summarize new test failure mechanisms in NVMs and associated test challenges. We also propose new test methodologies, test patterns and Design-for-Test (DFT) techniques to characterize new failure models and compress test time.