Test challenges and solutions for emerging non-volatile memories

Mohammad Nasim Imtiaz Khan, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising non-volatile memories (NVMs) are being investigated by the scientific community to address the issue. Some of the NVMs such as Spin-Transfer Torque RAM, Magnetic RAM, Resistive RAM, Phase Change Memory and Ferroelectric RAM have already entered the mainstream computing. However, the unique characteristics of these NVMs bring new fault models such as statistical and stochastic retention failures, magnetic and thermal tolerance failures, voltage droop and ground bounce induced read and write failures and long latency failures. In this work, we summarize new test failure mechanisms in NVMs and associated test challenges. We also propose new test methodologies, test patterns and Design-for-Test (DFT) techniques to characterize new failure models and compress test time.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018
PublisherIEEE Computer Society
Pages1-6
Number of pages6
ISBN (Electronic)9781538637746
DOIs
StatePublished - May 29 2018
Event36th IEEE VLSI Test Symposium, VTS 2018 - San Francisco, United States
Duration: Apr 22 2018Apr 25 2018

Publication series

NameProceedings of the IEEE VLSI Test Symposium
Volume2018-April

Other

Other36th IEEE VLSI Test Symposium, VTS 2018
CountryUnited States
CitySan Francisco
Period4/22/184/25/18

Fingerprint

Random access storage
Data storage equipment
Phase change memory
Ferroelectric materials
Torque
Silicon
Electric potential

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Khan, M. N. I., & Ghosh, S. (2018). Test challenges and solutions for emerging non-volatile memories. In Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018 (pp. 1-6). (Proceedings of the IEEE VLSI Test Symposium; Vol. 2018-April). IEEE Computer Society. https://doi.org/10.1109/VTS.2018.8368632
Khan, Mohammad Nasim Imtiaz ; Ghosh, Swaroop. / Test challenges and solutions for emerging non-volatile memories. Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018. IEEE Computer Society, 2018. pp. 1-6 (Proceedings of the IEEE VLSI Test Symposium).
@inproceedings{368c7995a3d64223ba2212ed424013f8,
title = "Test challenges and solutions for emerging non-volatile memories",
abstract = "At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising non-volatile memories (NVMs) are being investigated by the scientific community to address the issue. Some of the NVMs such as Spin-Transfer Torque RAM, Magnetic RAM, Resistive RAM, Phase Change Memory and Ferroelectric RAM have already entered the mainstream computing. However, the unique characteristics of these NVMs bring new fault models such as statistical and stochastic retention failures, magnetic and thermal tolerance failures, voltage droop and ground bounce induced read and write failures and long latency failures. In this work, we summarize new test failure mechanisms in NVMs and associated test challenges. We also propose new test methodologies, test patterns and Design-for-Test (DFT) techniques to characterize new failure models and compress test time.",
author = "Khan, {Mohammad Nasim Imtiaz} and Swaroop Ghosh",
year = "2018",
month = "5",
day = "29",
doi = "10.1109/VTS.2018.8368632",
language = "English (US)",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
pages = "1--6",
booktitle = "Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018",
address = "United States",

}

Khan, MNI & Ghosh, S 2018, Test challenges and solutions for emerging non-volatile memories. in Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018. Proceedings of the IEEE VLSI Test Symposium, vol. 2018-April, IEEE Computer Society, pp. 1-6, 36th IEEE VLSI Test Symposium, VTS 2018, San Francisco, United States, 4/22/18. https://doi.org/10.1109/VTS.2018.8368632

Test challenges and solutions for emerging non-volatile memories. / Khan, Mohammad Nasim Imtiaz; Ghosh, Swaroop.

Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018. IEEE Computer Society, 2018. p. 1-6 (Proceedings of the IEEE VLSI Test Symposium; Vol. 2018-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Test challenges and solutions for emerging non-volatile memories

AU - Khan, Mohammad Nasim Imtiaz

AU - Ghosh, Swaroop

PY - 2018/5/29

Y1 - 2018/5/29

N2 - At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising non-volatile memories (NVMs) are being investigated by the scientific community to address the issue. Some of the NVMs such as Spin-Transfer Torque RAM, Magnetic RAM, Resistive RAM, Phase Change Memory and Ferroelectric RAM have already entered the mainstream computing. However, the unique characteristics of these NVMs bring new fault models such as statistical and stochastic retention failures, magnetic and thermal tolerance failures, voltage droop and ground bounce induced read and write failures and long latency failures. In this work, we summarize new test failure mechanisms in NVMs and associated test challenges. We also propose new test methodologies, test patterns and Design-for-Test (DFT) techniques to characterize new failure models and compress test time.

AB - At the end of Silicon roadmap, keeping the leakage power in tolerable limit has become one of the biggest challenges. Several promising non-volatile memories (NVMs) are being investigated by the scientific community to address the issue. Some of the NVMs such as Spin-Transfer Torque RAM, Magnetic RAM, Resistive RAM, Phase Change Memory and Ferroelectric RAM have already entered the mainstream computing. However, the unique characteristics of these NVMs bring new fault models such as statistical and stochastic retention failures, magnetic and thermal tolerance failures, voltage droop and ground bounce induced read and write failures and long latency failures. In this work, we summarize new test failure mechanisms in NVMs and associated test challenges. We also propose new test methodologies, test patterns and Design-for-Test (DFT) techniques to characterize new failure models and compress test time.

UR - http://www.scopus.com/inward/record.url?scp=85048357078&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048357078&partnerID=8YFLogxK

U2 - 10.1109/VTS.2018.8368632

DO - 10.1109/VTS.2018.8368632

M3 - Conference contribution

AN - SCOPUS:85048357078

T3 - Proceedings of the IEEE VLSI Test Symposium

SP - 1

EP - 6

BT - Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018

PB - IEEE Computer Society

ER -

Khan MNI, Ghosh S. Test challenges and solutions for emerging non-volatile memories. In Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018. IEEE Computer Society. 2018. p. 1-6. (Proceedings of the IEEE VLSI Test Symposium). https://doi.org/10.1109/VTS.2018.8368632