Test generation for precise interrupts on out-of-order microprocessors

Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Validation of precise interrupts on a modern pipelined processor is a non-trivial task. The common approach of asserting external interrupts at random test points offers insufficient coverage, and exhaustive simulation under all pipeline conditions is grossly impractical. This paper describes an enhanced technique for effective verification of a pipelined processor in the event of external interrupts. The paper develops a framework to identify critical points in a test program when resource conflicts and inter-instruction dependencies are large. It is argued that if an external interrupt asserted at the identified points in the test program, then the likelihood of exposing design errors increases.

Original languageEnglish (US)
Title of host publication10th International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009
Pages79-82
Number of pages4
DOIs
StatePublished - 2009
Event10th International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009 - Austin, TX, United States
Duration: Dec 7 2009Dec 9 2009

Other

Other10th International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009
CountryUnited States
CityAustin, TX
Period12/7/0912/9/09

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Singh, P., Landis, D. L., & Narayanan, V. (2009). Test generation for precise interrupts on out-of-order microprocessors. In 10th International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009 (pp. 79-82). [5460806] https://doi.org/10.1109/MTV.2009.14