Abstract
Validation of precise interrupts on a modern pipelined processor is a non-trivial task. The common approach of asserting external interrupts at random test points offers insufficient coverage, and exhaustive simulation under all pipeline conditions is grossly impractical. This paper describes an enhanced technique for effective verification of a pipelined processor in the event of external interrupts. The paper develops a framework to identify critical points in a test program when resource conflicts and inter-instruction dependencies are large. It is argued that if an external interrupt asserted at the identified points in the test program, then the likelihood of exposing design errors increases.
Original language | English (US) |
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Title of host publication | 10th International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009 |
Pages | 79-82 |
Number of pages | 4 |
DOIs | |
State | Published - 2009 |
Event | 10th International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009 - Austin, TX, United States Duration: Dec 7 2009 → Dec 9 2009 |
Other
Other | 10th International Workshop on Microprocessor Test and Verification: Common Challenges and Solutions, MTV 2009 |
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Country | United States |
City | Austin, TX |
Period | 12/7/09 → 12/9/09 |
All Science Journal Classification (ASJC) codes
- Engineering(all)