TY - GEN

T1 - Test generation in circuits constructed by input decomposition

AU - Lee, Gueesang

AU - Irwin, Mary Jane

AU - Owens, Robert Michael

PY - 1990/9

Y1 - 1990/9

N2 - The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.

AB - The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.

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M3 - Conference contribution

AN - SCOPUS:0025486956

SN - O81862079X

T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

SP - 107

EP - 111

BT - Proceedings - IEEE International Conference on Computer Design

PB - Publ by IEEE

T2 - Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90

Y2 - 17 September 1990 through 19 September 1990

ER -