Test generation in circuits constructed by input decomposition

Gueesang Lee, Mary Jane Irwin, Robert Michael Owens

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
PublisherPubl by IEEE
Pages107-111
Number of pages5
ISBN (Print)O81862079X
StatePublished - Sep 1 1990
EventProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
Duration: Sep 17 1990Sep 19 1990

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

OtherProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
CityCambridge, MA, USA
Period9/17/909/19/90

Fingerprint

Decomposition
Networks (circuits)
Communication

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lee, G., Irwin, M. J., & Owens, R. M. (1990). Test generation in circuits constructed by input decomposition. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 107-111). (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). Publ by IEEE.
Lee, Gueesang ; Irwin, Mary Jane ; Owens, Robert Michael. / Test generation in circuits constructed by input decomposition. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. pp. 107-111 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).
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abstract = "The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.",
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Lee, G, Irwin, MJ & Owens, RM 1990, Test generation in circuits constructed by input decomposition. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Publ by IEEE, pp. 107-111, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 9/17/90.

Test generation in circuits constructed by input decomposition. / Lee, Gueesang; Irwin, Mary Jane; Owens, Robert Michael.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. p. 107-111 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - The logic synthesis tool FACTOR generates circuits by finding the best decomposition of the inputs to minimize the communication complexity. It tries to minimize the number of connections in the circuit, instead of the number of gates, for area optimization. In addition to the area optimization, FACTOR also has the feature of generating circuits for which test vectors can be easily generated. Because it tries to find an input partitioning which provides the minimal number of connections between subcircuits, the generated circuits are tree-type with restricted reconvergent fanouts. It is shown how improved testability can be achieved at the same time as area optimization by presenting an efficient test generation algorithm for the restricted tree-type circuits generated by FACTOR using single stuck-type fault model.

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Lee G, Irwin MJ, Owens RM. Test generation in circuits constructed by input decomposition. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE. 1990. p. 107-111. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).