TY - GEN
T1 - Test of Supply Noise for Emerging Non-Volatile Memory
AU - Khan, Mohammad Nasim Imtiaz
AU - Ghosh, Swaroop
N1 - Funding Information:
This work is supported by Semiconductor Research Corp. (2847.001), NSF (CNS-1722557, CNS-1814710, CCF-1718474, DGE-1723687, and DGE-1821766) and DARPA Young Faculty Award (D15AP00089).
Publisher Copyright:
© 2018 IEEE.
PY - 2019/1/23
Y1 - 2019/1/23
N2 - Emerging Non-Volatile Memories (NVMs) suffer from high read/write current which can result in supply noise such as voltage droop and ground bounce. The magnitude of supply noise depends on the old data and the new data that is being written (for a write operation) or the stored data (for a read operation). In prior work, it has been shown that the noise generated by one access can affect another parallel access. Therefore, parallel read/write operation should be tested considering the supply noise. However, testing for read/write failure with supply noise considerations can take significant test time. In this work, we show that test time can be reduced by 410.82X for RRAM-based NVM Last Level Cache (LLC) by using Design for Test (DFT) circuits such as wordline overdrive and ending write operation early. We also show that the proposed test can save 79.875J of energy compared to the baseline test method.
AB - Emerging Non-Volatile Memories (NVMs) suffer from high read/write current which can result in supply noise such as voltage droop and ground bounce. The magnitude of supply noise depends on the old data and the new data that is being written (for a write operation) or the stored data (for a read operation). In prior work, it has been shown that the noise generated by one access can affect another parallel access. Therefore, parallel read/write operation should be tested considering the supply noise. However, testing for read/write failure with supply noise considerations can take significant test time. In this work, we show that test time can be reduced by 410.82X for RRAM-based NVM Last Level Cache (LLC) by using Design for Test (DFT) circuits such as wordline overdrive and ending write operation early. We also show that the proposed test can save 79.875J of energy compared to the baseline test method.
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U2 - 10.1109/TEST.2018.8624896
DO - 10.1109/TEST.2018.8624896
M3 - Conference contribution
AN - SCOPUS:85062407282
T3 - Proceedings - International Test Conference
BT - International Test Conference 2018, ITC 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 49th IEEE International Test Conference, ITC 2018
Y2 - 29 October 2018 through 1 November 2018
ER -