The arithmetic cube II: A second generation VLSI DSP processor

Mary Jane Irwin, Robert M. Owens, Thomas P. Kelliher, Kin Ki Leung, Mohan Vishwanath

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A description is given of the synthesis, design, and simulation of the arithmetic cube II, a second-generation, high-performance digital signal processing architecture. The architecture implements the so-called small-n algorithms. The authors are currently building a prototype system which should be capable of computing a 1024 point complex DFT in 410 μs.

Original languageEnglish (US)
Title of host publicationProceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
Editors Anon
PublisherPubl by IEEE
Pages1125-1128
Number of pages4
Volume2
ISBN (Print)078030033
StatePublished - 1991
EventProceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91 - Toronto, Ont, Can
Duration: May 14 1991May 17 1991

Other

OtherProceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91
CityToronto, Ont, Can
Period5/14/915/17/91

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering
  • Acoustics and Ultrasonics

Fingerprint Dive into the research topics of 'The arithmetic cube II: A second generation VLSI DSP processor'. Together they form a unique fingerprint.

Cite this