The Design and Implementation of the Arithmetic Cube II, a VLSI Signal Processing System

Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder S. Bajwa, Wen Lin Yang

Research output: Contribution to journalArticle

Abstract

The Arithmetic Cube II is a high performance signal processing system designed and built at Penn State University. The architecture implements the so-called small-n algorithms, and is the first system making use of this approach to signal processing. The system is capable of computing a 1008 point complex-in complex-out DFT in 3.54 ms. This high performance rate is achieved using very modest technology (2 micron CMOS). This paper provides an overview of the small-n algorithms, then describes the architectural design and implementation of the system, the transform development environment, and reports results of operating the system.

Original languageEnglish (US)
Pages (from-to)491-502
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume1
Issue number4
DOIs
StatePublished - Dec 1993

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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