The Design of Error Checkers for Self-Checking Residue Number Arithmetic

W. Kenneth Jenkins

Research output: Contribution to journalArticle

50 Citations (Scopus)

Abstract

During the last few years residue number (RNS) arithmetic has gained increasing importance for providing high speed fault tolerant performance in dedicated digital signal processors. One factor that has limited the use of redundant RNS theory in practice is the hardware complexity of the error checker. This paper presents a mathematical analysis of the error correction algorithm which suggests a new design with considerably reduced hardware complexity. A hardward architecture for a high speed pipelined error checker is proposed.

Original languageEnglish (US)
Pages (from-to)388-396
Number of pages9
JournalIEEE Transactions on Computers
VolumeC-32
Issue number4
DOIs
StatePublished - 1983

Fingerprint

High Speed
Hardware
Digital Signal Processor
Digital signal processors
Error correction
Error Correction
Mathematical Analysis
Fault-tolerant
Design
Architecture

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Software
  • Theoretical Computer Science
  • Electrical and Electronic Engineering

Cite this

Jenkins, W. Kenneth. / The Design of Error Checkers for Self-Checking Residue Number Arithmetic. In: IEEE Transactions on Computers. 1983 ; Vol. C-32, No. 4. pp. 388-396.
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The Design of Error Checkers for Self-Checking Residue Number Arithmetic. / Jenkins, W. Kenneth.

In: IEEE Transactions on Computers, Vol. C-32, No. 4, 1983, p. 388-396.

Research output: Contribution to journalArticle

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