During the last few years residue number (RNS) arithmetic has gained increasing importance for providing high speed fault tolerant performance in dedicated digital signal processors. One factor that has limited the use of redundant RNS theory in practice is the hardware complexity of the error checker. This paper presents a mathematical analysis of the error correction algorithm which suggests a new design with considerably reduced hardware complexity. A hardward architecture for a high speed pipelined error checker is proposed.
All Science Journal Classification (ASJC) codes
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science
- Electrical and Electronic Engineering