Programmable logic controllers (PLC) are used extensively for controlling discrete processes. The PLC's versatility is based on its reprogrammability, but this versatility is bought at the expense of program correctness and verification. Modifications to existing PLC programs, or generation of new ones, requires the use of the controller and the hardware associated with it in order to debug the new instructions. This leads to a greatly increased program design cycle as equipment down-times must be scheduled to accommodate debugging. At the same time, testing uncertain instructions on the plant floor places all the hardware connected to the PLC in jeopardy of damage due to program errors. This paper presents the development of a generic personal computer (PC) based PLC simulator. The development of the simulator comprises two stages: one for the creation of the virtual PLC and the other for the manipulation of this virtual PLC. The virtual PLC comprises a lexical analyser and a parser which function as a 'compiler', checking syntax, and recognizing commands of the PLC language, and creating the internal representation of the PLC in the PC's memory which interacts with a graphical interface to allow interaction with the virtual PLC. Program verification is then performed on the emulator instead of on the actual controller, thus both decreasing the debugging time for new instructions and protecting the hardware on the shop floor. The technique is not specific to any particular system, and may be applied genetically to any controller.
All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
- Management Science and Operations Research
- Strategy and Management